
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 123
PIC18F6X2X/8X2X
FIGURE 10-17:
MCLR/V
PP
/RG5 PIN BLOCK DIAGRAM
TABLE 10-13: PORTG FUNCTIONS
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
MCLR/V
PP
/RG5
Data Bus
RD PORTA
RD LATA
Schmitt
Trigger
MCLRE
RD TRISA
Q
D
EN
Latch
Filter
Low Level
MCLR Detect
High Voltage Detect
Internal MCLR
HV
Name
Bit#
Buffer Type
Function
RG0/CCP3/P3A
bit 0
ST
Input/output port pin, Capture3 input/Compare3 output/PWM3 output,
or Enhanced PWM3 output P3A.
Input/output port pin, Addressable USART2 Asynchronous Transmit, or
Addressable USART2 Synchronous Clock.
Input/output port pin, Addressable USART2 Asynchronous Receive, or
Addressable USART2 Synchronous Data.
Input/output port pin, Capture4 input/Compare4 output/PWM4 output,
or Enhanced PWM3 output P3D.
Input/output port pin, Capture5 input/Compare5 output/PWM5 output,
or Enhanced PWM1 output P1D.
Master Clear input or programming voltage input (if MCLR is enabled).
Input only port pin or programming voltage input (if MCLR is
disabled).
RG1/TX2/CK2
bit 1
ST
RG2/RX2/DT2
bit 2
ST
RG3/CCP4/P3D
bit 3
ST
RG4/CCP5/P1D
bit 4
ST
MCLR/V
PP
/RG5
bit 5
ST
Legend:
ST = Schmitt Trigger input
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
PORTG
LATG
TRISG
Legend:
Note 1:
—
—
—
—
—
—
RG5
(1)
—
—
Read PORTG pin/Write PORTG Data Latch
LATG Data Output Register
Data Direction Control Register for PORTG
--0x xxxx
---x xxxx
--0u uuuu
---u uuuu
---1 1111
---1 1111
x
= unknown,
u
= unchanged
RG5 is available as an input only when MCLR is disabled.