PIC18F6X2X/8X2X
DS39612A-page 312
Advance Information
2003 Microchip Technology Inc.
SLEEP
Example:
Before Instruction
TO
PD =
After Instruction
TO
PD =
SUBFWB
Enter SLEEP mode
Syntax:
Operands:
Operation:
[
label
] SLEEP
None
00h
→
WDT,
0
→
WDT postscaler,
1
→
TO,
0
→
PD
TO, PD
Status Affected:
Encoding:
Description:
0000
0000
0000
0011
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
1
1
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
Q4
Go to
SLEEP
Decode
operation
Process
Data
SLEEP
=
=
1
0
If WDT causes wake-up, this bit is cleared.
Subtract f from W with borrow
Syntax:
Operands:
[
label
] SUBFWB f [,d [,a]
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
(W) – (f) – (C)
→
dest
N, OV, C, DC, Z
Operation:
Status Affected:
Encoding:
Description:
0101
01da
ffff
ffff
Subtract register ‘f’ and carry flag
(borrow) from W (2’s complement
method). If ‘d’ is 0, the result is
stored in W. If ‘d’ is 1, the result is
stored in register ‘f’ (default). If ‘a(chǎn)’ is
0, the Access Bank will be selected,
overriding the BSR value. If ‘a(chǎn)’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Q4
Decode
Process
Data
Write to
destination
Example 1:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
Example 2:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
Example 3:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
SUBFWB REG, 1, 0
=
=
=
3
2
1
=
=
=
=
=
FF
2
0
0
1 ; result is negative
SUBFWB REG, 0, 0
=
=
=
2
5
1
=
=
=
=
=
2
3
1
0
0 ; result is positive
SUBFWB REG, 1, 0
=
=
=
1
2
0
=
=
=
=
=
0
2
1
1 ; result is zero
0