參數(shù)資料
型號(hào)： PIC18F67J11T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 51/107頁
文件大小： 0K
描述： IC PIC MCU FLASH 64KX16 64TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 3930 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 帶卷 (TR)
配用： AC162091-ND - HEADER MPLAB ICD2 18F87J11 64/80
MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
AC164327-ND - MODULE SKT FOR 64TQFP
其它名稱： PIC18F67J11T-I/PTTR
PIC18F87J11 FAMILY
DS39778E-page 48
2007-2012 Microchip Technology Inc.
4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its status:
OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In
general, only one of these bits will be set while in a given
power-managed mode. When the OSTS bit is set, the
primary clock is providing the device clock. When the
T1RUN bit is set, the Timer1 oscillator is providing the
clock. If neither of these bits is set, INTRC is clocking the
device.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP
instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
for details). In this mode, the OSTS bit is set (see
).
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1). The primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet run-
ning, device clocks will be delayed until the
oscillator has started. In such situations, ini-
tial oscillator operation is far from stable and
unpredictable operation may result.
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