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參數(shù)資料
| 型號： | PIC18F6722T-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 64TQFP |
| 產品培訓模塊： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 標準包裝： | 1,200 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器容量： | 128KB（64K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.2 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 12x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 帶卷 (TR) |
| 配用： | MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11 |
PIC18F6627/6722/8627/8722
DS80221C-page 6
2006 Microchip Technology Inc.
16. Module: External Memory Bus
For PIC18F8XXX devices, the Stack Pointer may
incorrectly increment during a table read operation if
external memory bus wait states are enabled (i.e.,
Configuration bit, WAIT, is clear (CONFIG3L<7> = 0)
and WAIT<1:0> bits (MEMCON<5:4>) are not equal
to ‘11’).
Work around
If using the external memory bus and performing
TBLRD
operations
with
a
non-zero
wait
state (CONFIG3L<7>
=
0
and
WAIT<1:0>
(MEMCON<5:4> are not equal to ‘11’), disable
interrupts by clearing the GIE/GIEH (INTCON<7>)
and
PEIE/GIEL
(INTCON<6>)
bits
prior
to
executing any TBLRD operation.
17. Module: MSSP
In an I2C system with multiple slave nodes, an
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and SSPOV bits. In both
situations, the SSPxIF bit is not set and an inter-
rupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I2C slave must clear the SSPOV bit after each
I2C address match to maintain normal operation.
18. Module: MSSP
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is idle
when ACKEN, RCEN, PEN, RSEN, and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bits will be clear, indicating the bus is idle.
Clearing and setting the SSPEN bit will also reset
the I2C peripheral and clear the PEN, RSEN and
SEN status bits.
19. Module: MSSP
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL in SSPxCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPxCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
20. Module: MSSP
In I2C Master mode, the BRG value of ‘0’ may not
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPxADD
≥ ‘1’.
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