參數(shù)資料
型號： PIC18F6720T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 147/165頁
文件大?。?/td> 0K
描述： IC MCU FLASH 64KX16 W/AD 64-TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 25MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 3.75K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 帶卷 (TR)
配用： MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 80
2004 Microchip Technology Inc.
REGISTER 7-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program/Data EEPROM Memory Select bit
1
= Access Flash program memory
0
= Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1
= Access configuration or calibration registers
0
= Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0
= Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1
= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0
= The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1
= Allows write cycles to Flash program/data EEPROM
0
= Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1
= Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0
= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0
= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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