參數(shù)資料
      型號: PIC18F6720-I/PT
      廠商: Microchip Technology
      文件頁數(shù): 140/165頁
      文件大?。?/td> 0K
      描述: IC MCU FLASH 64KX16 EE 64TQFP
      產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
      8-bit PIC® Microcontroller Portfolio
      標(biāo)準(zhǔn)包裝: 160
      系列: PIC® 18F
      核心處理器: PIC
      芯體尺寸: 8-位
      速度: 25MHz
      連通性: I²C,SPI,UART/USART
      外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
      輸入/輸出數(shù): 52
      程序存儲器容量: 128KB(64K x 16)
      程序存儲器類型: 閃存
      EEPROM 大?。?/td> 1K x 8
      RAM 容量: 3.75K x 8
      電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
      數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
      振蕩器型: 外部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 64-TQFP
      包裝: 托盤
      配用: MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
      XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
      AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
      PIC18F6520/8520/6620/8620/6720/8720
      DS39609B-page 74
      2004 Microchip Technology Inc.
      6.2.2
      16-BIT WORD WRITE MODE
      Figure 6-2 shows an example of 16-bit Word Write
      mode for PIC18F8X20 devices. This mode is used for
      word-wide memories, which includes some of the
      EPROM and Flash type memories. This mode allows
      opcode fetches and table reads from all forms of 16-bit
      memory and table writes to any type of word-wide
      external memories. This method makes a distinction
      between TBLWT cycles to even or odd addresses.
      During
      a
      TBLWT
      cycle
      to
      an
      even
      address
      (TBLPTR<0> = 0), the TABLAT data is transferred to a
      holding latch and the external address data bus is
      tri-stated for the data portion of the bus cycle. No write
      signals are activated.
      During
      a
      TBLWT
      cycle
      to
      an
      odd
      address
      (TBLPTR<0> = 1), the TABLAT data is presented on
      the upper byte of the AD15:AD0 bus. The contents of
      the holding latch are presented on the lower byte of the
      AD15:AD0 bus.
      The WRH signal is strobed for each write cycle; the
      WRL pin is unused. The signal on the BA0 pin indicates
      the LSb of TBLPTR, but it is left unconnected. Instead,
      the UB and LB signals are active to select both bytes.
      The obvious limitation to this method is that the table
      write must be done in pairs on a specific word boundary
      to correctly write a word location.
      FIGURE 6-2:
      16-BIT WORD WRITE MODE EXAMPLE
      AD<7:0>
      PIC18F8X20
      AD<15:8>
      ALE
      373
      A<20:1>
      373
      OE
      WRH
      A<19:16>
      A<x:0>
      D<15:0>
      OE
      WR(1)
      CE
      D<15:0>
      JEDEC Word
      EPROM Memory
      Address Bus
      Data Bus
      Control Lines
      Note 1:
      This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
      CE
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