參數(shù)資料
型號： PIC18F66K90T-I/PTRSL
廠商： Microchip Technology
文件頁數(shù)： 30/110頁
文件大小： 0K
描述： MCU 8BIT 64K FLASH 64-TQFP
標準包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 帶卷 (TR)
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 477
PIC18F47J53 FAMILY
CPFSGT
Compare f with W, Skip if f > W
Syntax:
CPFSGT
f {,a}
Operands:
0
f 255
a
[0,1]
Operation:
(f) –
W),
skip if (f) > (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
010a
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CPFSGT REG, 0
NGREATER
:
GREATER
:
Before Instruction
PC
=
Address (HERE)
W=
?
After Instruction
If REG
W;
PC
=
Address (GREATER)
If REG
W;
PC
=
Address (NGREATER)
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSLT
f {,a}
Operands:
0
f 255
a
[0,1]
Operation:
(f) –
W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
000a
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CPFSLT REG, 1
NLESS
:
LESS
:
Before Instruction
PC
=
Address (HERE)
W=
?
After Instruction
If REG
<
W;
PC
=
Address (LESS)
If REG
W;
PC
=
Address (NLESS)
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