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參數(shù)資料
| 型號： | PIC18F66J93T-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 27/54頁 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 64KB 64-TQFP |
| 產(chǎn)品培訓模塊： | PIC18 J Series MCU Overview |
| 標準包裝： | 1,200 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復位，LCD，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3923 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 帶卷 (TR) |
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2009 Microchip Technology Inc.
Preliminary
DS39948A-page 31
PIC18F87J93 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1.
Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion:
Set GO/DONE bit (ADCON0<1>)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.
7.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 2-2:
ANALOG INPUT MODEL
VAIN
CPIN
RS
ANx
5 pF
VDD
VT = 0.6V
ILEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD = 25 pF
VSS
Sampling Switch
12
3
4
(k
Ω)
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch Resistance
RSS
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