2006 Microchip Technology Inc.
Advance Information
DS39762A-page 81
PIC18F97J60 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F97J60 FAMILY)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on
POR, BOR
Details on
page:
TOSU
—
—
—
Top-of-Stack Register Upper Byte (TOS<20:16>)
---0 0000
59, 71
TOSH
Top-of-Stack Register High Byte (TOS<15:8>)
0000 0000
59, 71
TOSL
Top-of-Stack Register Low Byte (TOS<7:0>)
STKFUL
(1)
STKUNF
(1)
0000 0000
59, 71
STKPTR
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
59, 72
PCLATU
—
—
bit 21
(2)
Holding Register for PC<20:16>
---0 0000
59, 71
PCLATH
Holding Register for PC<15:8>
0000 0000
59, 71
PCL
PC Low Byte (PC<7:0>)
0000 0000
59, 71
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
59, 98
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
59, 98
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
59, 98
TABLAT
Program Memory Table Latch
0000 0000
59, 98
PRODH
Product Register High Byte
xxxx xxxx
59, 117
PRODL
Product Register Low Byte
xxxx xxxx
59, 117
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
59, 121
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
59, 122
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
59, 123
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
59, 89
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
59, 90
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
59, 90
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
59, 90
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
59, 90
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx
59, 89
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
59, 90
WREG
Working Register
xxxx xxxx
59
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
59, 89
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
59, 90
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
59, 90
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
59, 90
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
59, 90
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx
59, 89
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
59, 89
BSR
—
—
—
—
Bank Select Register
---- 0000
59, 89
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
59, 89
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
59, 90
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
59, 90
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
59, 90
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
59, 90
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx
59, 89
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
59, 89
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented, read as ‘
0
’,
q
= value depends on condition, r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘
0
’.
Note 1:
Bit 7 and bit 6 are cleared by user software or by a POR.
2:
Bit 21 of the PC is only available in Serial Programming modes.
3:
Reset value is ‘
0
’ when Two-Speed Start-up is enabled and ‘
1
’ if disabled.
4:
Alternate names and definitions for these bits when the MSSP module is operating in I
2
C Slave mode.
5:
These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset values shown
apply only to 100-pin devices.
6:
These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘
0
’. Reset
values are shown for 100-pin devices.
7:
In Microcontroller mode, the bits in this register are unwritable and read as ‘
0
’.
8:
PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘
0
’.
9:
Implemented in 100-pin devices in Microcontroller mode only.