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PIC18F87J50 FAMILY
DS39775B-page 464
Preliminary
2007 Microchip Technology Inc.
Brown-out Reset (BOR) .....................................................55
and On-Chip Voltage Regulator ...............................359
Detecting ....................................................................55
Disabling in Sleep Mode ............................................55
BSF ..................................................................................375
BTFSC .............................................................................376
BTFSS ..............................................................................376
BTG ..................................................................................377
BZ .....................................................................................378
C
C Compilers
MPLAB C18 .............................................................414
MPLAB C30 .............................................................414
Calibration (A/D Converter) ..............................................307
CALL ................................................................................378
CALLW .............................................................................407
Capture (CCP Module) .....................................................209
Associated Registers ...............................................211
CCPRxH:CCPRxL Registers ...................................209
CCPx Pin Configuration ...........................................209
Prescaler ..................................................................209
Software Interrupt ....................................................209
Timer1/Timer3 Mode Selection ................................209
Capture (ECCP Module) ..................................................218
Capture/Compare/PWM (CCP) ........................................207
Capture Mode.
See
Capture.
CCP Mode and Timer Resources ............................208
CCPRxH Register ....................................................208
CCPRxL Register .....................................................208
Compare Mode.
See
Compare.
ECCP/CCP Timer Interconnect
Configurations ..................................................208
Module Configuration ...............................................208
Clock Sources ....................................................................40
Effects of Power-Managed Modes .............................44
Selecting the 31 kHz Source ......................................40
Selection Using OSCCON Register ...........................40
CLRF ................................................................................379
CLRWDT ..........................................................................379
Code Examples
16 x 16 Signed Multiply Routine ..............................118
16 x 16 Unsigned Multiply Routine ..........................118
8 x 8 Signed Multiply Routine ..................................117
8 x 8 Unsigned Multiply Routine ..............................117
A/D Calibration Routine ...........................................307
Changing Between Capture Prescalers ...................209
Computed GOTO Using an Offset Value ...................73
Erasing a Flash Program Memory Row ...................100
Fast Register Stack ....................................................73
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................88
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ...............................197
Initializing PORTA ....................................................138
Initializing PORTB ....................................................141
Initializing PORTC ....................................................144
Initializing PORTD ....................................................147
Initializing PORTE ....................................................150
Initializing PORTF ....................................................153
Initializing PORTG ...................................................156
Initializing PORTH ....................................................159
Initializing PORTJ ....................................................162
Loading the SSP1BUF (SSP1SR) Register .............234
Reading a Flash Program Memory Word ..................99
Saving STATUS, WREG and BSR
Registers in RAM ............................................. 134
Writing to Flash Program Memory ........................... 102
Code Protection ............................................................... 347
COMF .............................................................................. 380
Comparator ...................................................................... 335
Analog Input Connection Considerations ................ 338
Associated Registers ............................................... 342
Configuration ........................................................... 339
Control ..................................................................... 339
Effects of a Reset .................................................... 342
Enable and Input Selection ...................................... 339
Enable and Output Selection ................................... 339
Interrupts ................................................................. 341
Operation ................................................................. 338
Operation During Sleep ........................................... 342
Response Time ........................................................ 338
Comparator Specifications ............................................... 431
Comparator Voltage Reference ....................................... 343
Accuracy and Error .................................................. 345
Associated Registers ............................................... 345
Configuring .............................................................. 344
Connection Considerations ...................................... 345
Effects of a Reset .................................................... 345
Operation During Sleep ........................................... 345
Compare (CCP Module) .................................................. 210
Associated Registers ............................................... 211
CCPRx Register ...................................................... 210
Pin Configuration ..................................................... 210
Software Interrupt .................................................... 210
Timer1/Timer3 Mode Selection ................................ 210
Compare (ECCP Module) ................................................ 218
Special Event Trigger .............................. 203, 218, 306
Computed GOTO ............................................................... 73
Configuration Bits ............................................................ 347
Configuration Mismatch (CM) Reset .................................. 55
Configuration Register Protection .................................... 362
Core Features
Easy Migration ............................................................. 8
Expanded Memory ....................................................... 7
Extended Instruction Set ............................................. 8
External Memory Bus .................................................. 8
nanoWatt Technology .................................................. 7
Oscillator Options and Features .................................. 7
Universal Serial Bus (USB) .......................................... 7
CPFSEQ .......................................................................... 380
CPFSGT .......................................................................... 381
CPFSLT ........................................................................... 381
Crystal Oscillator/Ceramic Resonator ................................ 35
Customer Change Notification Service ............................ 474
Customer Notification Service ......................................... 474
Customer Support ............................................................ 474
D
Data Addressing Modes .................................................... 88
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 92
Direct ......................................................................... 88
Indexed Literal Offset ................................................ 91
BSR ................................................................... 93
Instructions Affected .......................................... 91
Mapping Access Bank ....................................... 93
Indirect ....................................................................... 88
Inherent and Literal .................................................... 88