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PIC18F87J11 FAMILY
DS39778B-page 442
Preliminary
2007 Microchip Technology Inc.
Timing Diagrams
A/D Conversion.........................................................420
Asynchronous Reception..........................................282
Asynchronous Transmission.....................................280
Asynchronous Transmission (Back to Back) ............280
Automatic Baud Rate Calculation .............................278
Auto-Wake-up Bit (WUE) During
Normal Operation..............................................283
Auto-Wake-up Bit (WUE) During Sleep ....................283
Baud Rate Generator with Clock Arbitration.............256
BRG Overflow Sequence..........................................278
BRG Reset Due to SDAx Arbitration During
Start Condition ..................................................265
Bus Collision During a Repeated Start Condition (Case
1).......................................................................266
Bus Collision During a Repeated Start
Condition (Case 2)............................................266
Bus Collision During a Start
Condition (SCLx = 0) ........................................265
Bus Collision During a Stop
Condition (Case 1)............................................267
Bus Collision During a Stop
Condition (Case 2)............................................267
Bus Collision During Start
Condition (SDAx Only)......................................264
Bus Collision for Transmit and Acknowledge............263
Capture/Compare/PWM (Including
ECCP Modules)................................................410
CLKO and I/O ...........................................................402
Clock Synchronization ..............................................249
Clock/Instruction Cycle ...............................................68
EUSART Synchronous Receive
(Master/Slave)...................................................419
EUSART Synchronous Transmission
(Master/Slave)...................................................419
Example SPI Master Mode (CKE = 0) ......................411
Example SPI Master Mode (CKE = 1) ......................412
Example SPI Slave Mode (CKE = 0) ........................413
Example SPI Slave Mode (CKE = 1) ........................414
External Clock (All Modes Except PLL) ....................400
External Memory Bus for Sleep (Extended
Microcontroller Mode)...............................104, 106
External Memory Bus for TBLRD (Extended
Microcontroller Mode)...............................104, 106
Fail-Safe Clock Monitor.............................................326
First Start Bit Timing .................................................257
Full-Bridge PWM Output...........................................215
Half-Bridge PWM Output ..........................................214
I
2
C Acknowledge Sequence .....................................262
I
2
C Bus Data.............................................................415
I
2
C Bus Start/Stop Bits..............................................415
I
2
C Master Mode (7 or 10-Bit Transmission) ............260
I
2
C Master Mode (7-Bit Reception)...........................261
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ...........246
I
2
C Slave Mode (10-Bit Reception,
SEN = 0, ADMSK = 01001) ..............................245
I
2
C Slave Mode (10-Bit Reception, SEN = 1) ...........251
I
2
C Slave Mode (10-Bit Transmission)......................247
I
2
C Slave Mode (7-Bit Reception, SEN = 0) .............242
I
2
C Slave Mode (7-bit Reception,
SEN = 0, ADMSK = 01011) ..............................243
I
2
C Slave Mode (7-Bit Reception, SEN = 1) .............250
I
2
C Slave Mode (7-Bit Transmission)........................244
I
2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode).........252
I
2
C Stop Condition Receive or Transmit Mode......... 262
MSSP I
2
C Bus Data.................................................. 417
MSSP I
2
C Bus Start/Stop Bits.................................. 417
Parallel Master Port Read......................................... 408
Parallel Master Port Write......................................... 409
Parallel Slave Port.................................................... 407
Parallel Slave Port Read................................... 166, 169
Parallel Slave Port Write................................... 166, 169
Program Memory Read ............................................ 403
Program Memory Write............................................. 404
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled)..................................... 220
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled)...................................... 220
PWM Direction Change............................................ 217
PWM Direction Change at Near
100% Duty Cycle.............................................. 217
PWM Output............................................................. 204
Read and Write, 8-Bit Data,
Demultiplexed Address..................................... 173
Read, 16-Bit Data, Demultiplexed Address.............. 176
Read, 16-Bit Muliplexed Data, Fully
Multiplexed 16-Bit Address............................... 177
Read, 16-Bit Multiplexed Data, Partially
Multiplexed Address ......................................... 176
Read, 8-Bit Data, Fully Multiplexed
16-Bit Address.................................................. 175
Read, 8-Bit Data, Partially Multiplexed Address....... 173
Read, 8-Bit Data, Partially Multiplexed
Address, Enable Strobe.................................... 174
Read, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address ........................... 173
Repeated Start Condition ......................................... 258
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT)...... 405
Send Break Character Sequence............................. 284
Slave Synchronization.............................................. 229
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
)............................................. 53
SPI Mode (Master Mode).......................................... 228
SPI Mode (Slave Mode, CKE = 0)............................ 230
SPI Mode (Slave Mode, CKE = 1)............................ 230
Synchronous Reception (Master Mode,
SREN) .............................................................. 287
Synchronous Transmission ...................................... 285
Synchronous Transmission (Through TXEN)........... 286
Time-out Sequence on Power-up (MCLR Not
Tied to V
DD
), Case 1 .......................................... 52
Time-out Sequence on Power-up (MCLR Not
Tied to V
DD
), Case 2 .......................................... 53
Time-out Sequence on Power-up (MCLR Tied
to V
DD
, V
DD
Rise < T
PWRT
) ................................ 52
Timer0 and Timer1 External Clock........................... 406
Transition for Entry to Idle Mode................................. 46
Transition for Entry to SEC_RUN Mode..................... 43
Transition for Entry to Sleep Mode............................. 45
Transition for Two-Speed Start-up
(INTRC to HSPLL)............................................ 324
Transition for Wake From Idle to Run Mode............... 46
Transition for Wake From Sleep (HSPLL).................. 45
Transition From RC_RUN Mode to
PRI_RUN Mode.................................................. 44
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL)................................... 43
Transition to RC_RUN Mode...................................... 44