
PIC18F6X2X/8X2X
DS39612A-page 38
Advance Information
2003 Microchip Technology Inc.
PORTJ
PORTH
PORTG
(7)
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
(5,6)
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
Legend:
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘0’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h
or
0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for RESET value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
If MCLR function is disabled, PORTG<5> is a read only bit.
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx uuuu
uuuu uuuu
uuuu uuuu
---x xxxx
---u uuuu
---u uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
-xxx 0000
(5)
uuuu uuuu
-uuu 0000
(5)
uuuu uuuu
-uuu uuuu
(5)
0000 0000
-1-0 0-00
0000 0000
-1-0 0-00
uuuu uuuu
-1-u u-uu
0000 0000
0000 0000
uuuu uuuu
-1-0 0-00
0000 0000
-1-0 0-00
0000 0000
-1-u u-uu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
1111 1111
-000 0000
1111 1111
-000 0000
uuuu uuuu
-uuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
--00 0000
xxxx xxxx
--00 0000
uuuu uuuu
--uu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
--00 0000
xxxx xxxx
--00 0000
uuuu uuuu
--uu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 -010
0000 -010
uuuu -u1u
0000 000x
0000 0000
0000 000x
0000 0000
uuuu uuu-
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6:
7: