參數(shù)資料
型號(hào)： PIC18F65K90T-I/MR
廠商： Microchip Technology
文件頁數(shù)： 25/110頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 32KB FLASH 64QFN
標(biāo)準(zhǔn)包裝： 3,300
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
PIC18F47J53 FAMILY
DS39964B-page 472
Preliminary
2010 Microchip Technology Inc.
BTFSC
Bit Test File, Skip if Clear
Syntax:
BTFSC f, b {,a}
Operands:
0
f 255
0
b 7
a
[0,1]
Operation:
skip if (f<b>) = 0
Status Affected:
None
Encoding:
1011
bbba
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected. If
‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (TRUE)
If FLAG<1>
=
1;
PC
=
address (FALSE)
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSS f, b {,a}
Operands:
0
f 255
0
b < 7
a
[0,1]
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
1010
bbba
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected. If
‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSS
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (FALSE)
If FLAG<1>
=
1;
PC
=
address (TRUE)
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