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    參數(shù)資料
    型號(hào): PIC18F65K90-I/MR
    廠商: Microchip Technology
    文件頁(yè)數(shù): 285/338頁(yè)
    文件大?。?/td> 0K
    描述: IC MCU 8BIT 32KB FLASH 64QFN
    產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 40
    系列: PIC® XLP™ 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 64MHz
    連通性: I²C,LIN,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
    輸入/輸出數(shù): 53
    程序存儲(chǔ)器容量: 32KB(16K x 16)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大?。?/td> 1K x 8
    RAM 容量: 2K x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 64-VFQFN 裸露焊盤
    包裝: 管件
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    PIC18F87K90 FAMILY
    DS39957D-page 50
    2009-2011 Microchip Technology Inc.
    3.6.2
    INTPLL MODES
    The 4x Phase Locked Loop (PLL) can be used with the
    HF-INTOSC to produce faster device clock speeds
    than are normally possible with the internal oscillator
    sources. When enabled, the PLL produces a clock
    speed of 32 MHz or 64 MHz.
    PLL operation is controlled through software. The con-
    trol bit, PLLEN (OSCTUNE<6>) is used to enable or
    disable its operation. Additionally, the PLL will only func-
    tion when the selected HF-INTOSC frequency is either
    8 MHz or 16 MHz (OSCCON<6:4> = 111 or 110).
    Like the INTIO modes, there are two distinct INTPLL
    modes available:
    In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
    while OSC1 functions as RA7 for digital input and
    output. Externally, this is identical in appearance
    to INTIO1 (Figure 3-8).
    In INTPLL2 mode, OSC1 functions as RA7 and
    OSC2 functions as RA6, both for digital input and
    output. Externally, this is identical to INTIO2
    3.6.3
    INTERNAL OSCILLATOR OUTPUT
    FREQUENCY AND TUNING
    The internal oscillator block is calibrated at the factory
    to produce an INTOSC output frequency of 16 MHz. It
    can be adjusted in the user’s application by writing to
    TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
    register (Register 3-3).
    When the OSCTUNE register is modified, the INTOSC
    (HF-INTOSC and MF-INTOSC) frequency will begin
    shifting to the new frequency. The oscillator will require
    some time to stabilize. Code execution continues
    during this shift and there is no indication that the shift
    has occurred.
    The LF-INTOSC oscillator operates independently of
    the HF-INTOSC or the MF-INTOSC source. Any
    changes in the HF-INTOSC or the MF-INTOSC source,
    across voltage and temperature, are not necessarily
    reflected by changes in LF-INTOSC or vice versa. The
    frequency of LF-INTOSC is not affected by OSCTUNE.
    3.6.4
    INTOSC FREQUENCY DRIFT
    The INTOSC frequency may drift as VDD or tempera-
    ture changes and can affect the controller operation in
    a variety of ways. It is possible to adjust the INTOSC
    frequency by modifying the value in the OSCTUNE
    register. Depending on the device, this may have no
    effect on the LF-INTOSC clock source frequency.
    Tuning INTOSC requires knowing when to make the
    adjustment, in which direction it should be made, and in
    some cases, how large a change is needed. Three
    compensation techniques are shown here.
    3.6.4.1
    Compensating with the EUSART
    An adjustment may be required when the EUSART
    begins to generate framing errors or receives data with
    errors while in Asynchronous mode. Framing errors
    indicate that the device clock frequency is too high. To
    adjust for this, decrement the value in OSCTUNE to
    reduce the clock frequency. On the other hand, errors
    in data may suggest that the clock speed is too low. To
    compensate, increment OSCTUNE to increase the
    clock frequency.
    3.6.4.2
    Compensating with the Timers
    This technique compares device clock speed to some
    reference clock. Two timers may be used; one timer is
    clocked by the peripheral clock, while the other is
    clocked by a fixed reference source, such as the SOSC
    oscillator.
    Both timers are cleared, but the timer clocked by the
    reference source generates interrupts. When an inter-
    rupt occurs, the internally clocked timer is read and
    both timers are cleared. If the internally clocked timer
    value is much greater than expected, then the internal
    oscillator block is running too fast. To adjust for this,
    decrement the OSCTUNE register.
    3.6.4.3
    Compensating with the CCP Module
    in Capture Mode
    A CCP module can use free-running Timer1 (or
    Timer3), clocked by the internal oscillator block and an
    external event with a known period (i.e., AC power
    frequency). The time of the first event is captured in the
    CCPRxH:CCPRxL registers and is recorded for use
    later. When the second event causes a capture, the
    time of the first event is subtracted from the time of the
    second event. Since the period of the external event is
    known, the time difference between events can be
    calculated.
    If the measured time is much greater than the
    calculated time, the internal oscillator block is running
    too fast. To compensate, decrement the OSCTUNE
    register. If the measured time is much less than the
    calculated time, the internal oscillator block is running
    too slow. To compensate, increment the OSCTUNE
    register.
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