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2010-2012 Microchip Technology Inc.
DS39977F-page 15
PIC18F66K80 FAMILY
FIGURE 1-1:
PIC18F2XK80 (28-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH
PCL
PCLATH
8
31-Level Stack
Program Counter
PRODL
PRODH
8 x 8 Multiply
8
BITOP
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
12
3
PCLATU
PCU
Note
1:
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator .
3:
RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
A/D
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
EUSART2
ROM Latch
PORTC
RC<7:0>(1)
PORTB
RB<7:0>(1)
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer 2/4
Timer 3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA<3:0>
RA<7:5>(1,2)
PORTE
RE3(1,3)
ECAN
MSSP
IR