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PIC18F8722 FAMILY
DS39646B-page 76
Preliminary
2004 Microchip Technology Inc.
TABLE 5-3:
REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
57, 66
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
57, 66
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL
(6)
STKUNF
(6)
0000 0000
57, 66
STKPTR
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
57, 67
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000
57, 66
PCLATH
Holding Register for PC<15:8>
0000 0000
57, 66
PCL
PC Low Byte (PC<7:0>)
0000 0000
57, 66
TBLPTRU
—
—
bit 21
(7)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
57, 90
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
57, 90
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
57, 90
TABLAT
Program Memory Table Latch
0000 0000
57, 90
PRODH
Product Register High Byte
xxxx xxxx
57, 117
PRODL
Product Register Low Byte
xxxx xxxx
57, 117
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
57, 121
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
57, 122
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
57, 123
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
57, 82
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
57, 82
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
57, 82
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
57, 82
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
57, 82
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000
57, 82
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
57, 82
WREG
Working Register
xxxx xxxx
57
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
57, 82
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
57, 82
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
57, 82
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
57, 82
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
57, 82
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- 0000
58, 82
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
58, 82
BSR
—
—
—
—
Bank Select Register
---- 0000
58, 72
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
58, 82
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
58, 82
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
58, 82
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
58, 82
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
58, 82
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000
58, 82
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
58, 82
Legend:
Note
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits =
01
; otherwise, this bit reads as ‘
0
’.
These registers and/or bits are not implemented on 64-pin devices and are read as
‘
0
’
. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘
-
’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
‘
0
’
. See
Section 2.6.4 “PLL in
INTOSC Modes”
.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘
0
’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit =
0
); otherwise, RG5 and LATG5 read as
‘
0
’
.
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device configuration bits.
1:
2:
3:
4:
5:
6:
7: