
PIC18F6525/6621/8525/8621
DS39612B-page 74
 2005 Microchip Technology Inc.
6.2.2
16-BIT WORD WRITE MODE
mode for PIC18F8525/8621 devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of word-
wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During
a
TBLWT
cycle
to
an
even
address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
During
a
TBLWT
cycle
to
an
odd
address
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
FIGURE 6-2:
16-BIT WORD WRITE MODE EXAMPLE
AD<7:0>
PIC18F8X2X
AD<15:8>
ALE
373
A<20:1>
373
OE
WRH
A<19:16>
A<x:0>
D<15:0>
OE
WR(1)
CE
D<15:0>
JEDEC Word
EPROM Memory
Address Bus
Data Bus
Control Lines
Note
1:
CE