
2007 Microchip Technology Inc.
Preliminary
DS39636C-page 265
PIC18F2X1X/4X1X
ANDWF
Example:
BC
AND W with f
Syntax:
ANDWF f {,d {,a}}
Operands:
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
(W) .AND. (f)
→
dest
Operation:
Status Affected:
N, Z
Encoding:
0001
01da
ffff
ffff
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘
0
’, the result is stored
in W. If ‘d’ is ‘
1
’, the result is stored back
in register ‘f’ (default).
If ‘a(chǎn)’ is ‘
0
’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘
1
’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘
0
’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤
95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
ANDWF
REG, 0, 0
Before Instruction
W
REG
After Instruction
W
REG
=
=
17h
C2h
=
=
02h
C2h
Branch if Carry
Syntax:
BC n
Operands:
-128
≤
n
≤
127
Operation:
if Carry bit is ‘
1
’
(PC) + 2 + 2n
→
PC
Status Affected:
None
Encoding:
1110
0010
nnnn
nnnn
Description:
If the Carry bit is ‘
1
’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
No
Decode
Read literal
‘n’
Process
Data
operation
Example:
HERE
BC
5
Before Instruction
PC
After Instruction
If Carry
=
address
(HERE)
=
=
=
=
1;
address
(HERE + 12)
0;
address
(HERE + 2)
PC
If Carry
PC