THLD
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F46K20-E/P
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 33/42闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC PIC MCU FLASH 32KX16 40-DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
瑕栭牷鏂囦欢锛� World's Lowest Power in Sleep MCU: nanoWatt XLP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� PIC® XLP™ 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 48MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 35
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 64KB锛�32K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.8K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 14x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 657 (CN2011-ZH PDF)
閰嶇敤锛� AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
DM164124-ND - KIT STARTER FOR PIC18F4XK20
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 39
PIC18F2XK20/4XK20
P12
THLD2
Input Data Hold Time from MCLR/VPP/RE3
鈫�
2鈥�
渭s
P13
TSET2VDD
鈫� Setup Time to MCLR/VPP/RE3 鈫�
100
鈥�
ns
P14
TVALID
Data Out Valid from PGC
鈫�
10
鈥�
ns
P15
TSET3PGM
鈫� Setup Time to MCLR/VPP/RE3 鈫�
2鈥�
渭s
P16
TDLY8
Delay between Last PGC
鈫� and MCLR/VPP/RE3 鈫�
0鈥�
s
P17
THLD3MCLR/VPP/RE3
鈫� to VDD 鈫�
鈥�
100
ns
P18
THLD4MCLR/VPP/RE3
鈫� to PGM 鈫�
0鈥�
s
P19
THIZ
Delay from PGC
鈫� to PGD High-Z
3
10
nS
P20
TPPDP
Hold time after VPP changes
5
鈥�
渭s
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25
掳C is recommended
Param
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1:
Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only)
+ 1.5
渭s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and
TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data
sheet for the particular device.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC18F46K20-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB Flash 3968B RAM 36 I/O 8B RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F46K20-I/MV 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968BRM 36I/O 8b Fam nanowatt XLP RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F46K20-I/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB Flash 3968B RAM 36 I/O 8B RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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PIC18F46K20T-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB Flash 3968B RAM 36 I/O 8B RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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