
PIC18F46J50 FAMILY
DS39931D-page 172
2011 Microchip Technology Inc.
REGISTER 11-3:
PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1)
R-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BUSY:
Busy bit (Master mode only)
1
= Port is busy
0
= Port is not busy
bit 6-5
IRQM<1:0>:
Interrupt Request Mode bits
11
= Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP
mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10
= No interrupt is generated, processor stall is activated
01
= Interrupt is generated at the end of the read/write cycle
00
= No interrupt is generated
bit 4-3
INCM<1:0>:
Increment Mode bits
11
= PSP read and write buffers auto-increment (Legacy PSP mode only)
10
= Decrement ADDR<15,13:0> by 1 every read/write cycle
01
= Increment ADDR<15,13:0> by 1 every read/write cycle
00
= No increment or decrement of the address
bit 2
MODE16:
8/16-Bit Mode bit
1
= 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers
0
= 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
bit 1-0
MODE<1:0>:
Parallel Port Mode Select bits
11
= Master Mode 1 (PMCS, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10
= Master Mode 2 (PMCS, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01
= Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)
00
= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
Note 1:
This register is only available on 44-pin devices.