PIC18C601/801
DS39541A-page 308
Advance Information
2001 Microchip Technology Inc.
C
CALL ................................................................................
230Capture (CCP Module) ....................................................
142Block Diagram .........................................................
143CCP Pin Configuration .............................................
142CCPR1H:CCPR1L Registers ...................................
142Changing Between Capture Prescalers ...................
143Software Interrupt ....................................................
143Timer1 Mode Selection ............................................
142Capture/Compare/PWM (CCP) .......................................
141CCP1 .......................................................................
142CCPR1H Register ...........................................
142CCPR1L Register ............................................
142CCP2 .......................................................................
142CCPR2H Register ...........................................
142CCPR2L Register ............................................
142Interaction of Two CCP Modules .............................
142Registers Associated with Capture
and Compare ...........................................
145Timer Resources .....................................................
142Timing Diagram .......................................................
282Chip Select
Chip Select 2 (CS2) ...................................................
71Chip Select I/O (CSIO) ......................................................
71Chip Selects
Chip Select 1 (CS1) ...................................................
71Clocking Scheme ...............................................................
46CLRF ...............................................................................
231CLRWDT .........................................................................
231Code Examples ...............................................................
154Changing Between Capture Prescalers ...................
143Clearing RAM Using Indirect Addressing ..................
59Combination Unlock (Macro) .....................................
51Combination Unlock (Subroutine) ..............................
50Fast Register Stack ...................................................
45Initializing PORTA ....................................................
103Initializing PORTB ....................................................
105Initializing PORTC ...................................................
108Initializing PORTD ...................................................
110Initializing PORTE ....................................................
113Initializing PORTF ....................................................
116Initializing PORTG ...................................................
119Initializing PORTH ...................................................
121Initializing PORTJ ....................................................
124Programming Chip Select Signals ...........................
116Saving STATUS, WREG and BSR Registers ..........
101Table Read ................................................................
75Table Write ................................................................
77COMF ..............................................................................
232Compare (CCP Module) ..................................................
144Block Diagram .........................................................
144CCP Pin Configuration .............................................
144CCPR1H:CCPR1L Registers ...................................
144Software Interrupt ....................................................
144Special Event Trigger ....................
133Timer1 Mode Selection ............................................
144Configuration Address Map, Example ...............................
71Configuration Bits ............................................................
207Table ........................................................................
207Context Saving During Interrupts .....................................
101CPFSEQ ..........................................................................
232CPFSGT ..........................................................................
233CPFSLT ...........................................................................
233D
Data Memory .....................................................................
49General Purpose Registers .......................................
49Special Function Registers ........................................
49Data Memory Map
Program Bit Not Set ..................................................
51Program Bit Set .........................................................
52DAW ................................................................................
234DC and AC Characteristics Graphs and Tables ..............
295DCFSNZ ..........................................................................
235DECF ...............................................................................
234DECFSZ ..........................................................................
235Development Support ......................................................
259Development Tool Version Requirements .......................
305Device Differences ..........................................................
303Device Migrations ............................................................
304Direct Addressing ..............................................................
60E
Electrical Characteristics .................................................
265Errata ...................................................................................
7External Wait Cycles .........................................................
72F
Fast Register Stack ...........................................................
45Firmware Instructions ......................................................
215G
General Call Address Sequence .....................................
162General Call Address Support .........................................
162GOTO ..............................................................................
236I
I/O Mode ..........................................................................
119I/O Ports ..........................................................................
103I2C (SSP Module) ............................................................ 159 ACK Pulse .......................................................
159Addressing ..............................................................
160Block Diagram .........................................................
159Read/Write Bit Information (R/W Bit) .......................
160Reception ................................................................
160Serial Clock (RC3/SCK/SCL) ..................................
160Slave Mode .............................................................
159Timing Diagram, Data .............................................
287Timing Diagram, START/STOP Bits .......................
287Transmission ...........................................................
160I2C Master Mode Reception ............................................ 167 I2C Master Mode RESTART Condition ........................... 166 I2C Module
Acknowledge Sequence Timing ..............................
170Baud Rate Generator ..............................................
164Block Diagram .................................................
164BRG Reset due to SDA Collision ............................
174BRG Timing .............................................................
165Bus Collision
Acknowledge ...................................................
172RESTART Condition .......................................
175RESTART Condition Timing (Case1) ..............
175RESTART Condition Timing (Case2) ..............
175START Condition ............................................
173START Condition Timing ........................
173STOP Condition ..............................................
176STOP Condition Timing (Case1) .....................
176STOP Condition Timing (Case2) .....................
176Transmit Timing ..............................................
172Bus Collision Timing ................................................
172