PIC18C601/801
DS39541A-page 312
Advance Information
2001 Microchip Technology Inc.
Program Counter
PCL Register .............................................................
46PCLATH Register ......................................................
46Program Memory ...............................................................
39Boot Loader ...............................................................
43Memory Map, PIC18C601
Program Bit Not Set ...........................................
40Program Bit Set .................................................
41Memory Map, PIC18C801
Program Bit Not Set ...........................................
40Program Bit Set .................................................
42Program Memory Map
PIC18C601 ................................................................
40Program Bit Set .................................................
41PIC18C801 ................................................................
40Program Bit Set .................................................
42Programming, Device Instructions ...................................
215PUSH ...............................................................................
244PWM (CCP Module) ........................................................
146Block Diagram .........................................................
146CCPR1H:CCPR1L Registers ...................................
146Duty Cycle ...............................................................
146Example Frequencies/Resolutions ..........................
147Output Diagram .......................................................
146Period ......................................................................
146Registers Associated with PWM ..............................
147Setup for PWM Operation ........................................
147TMR2 to PR2 Match .......................................
135Q
Q Clock ............................................................................
146R
RCALL .............................................................................
245RCSTA Register
SPEN Bit ..................................................................
177Reader Response ............................................................
316Register File .......................................................................
49Register File Summary ......................................................
54Registers
ADCON0 (A/D Control 0) .......................................... 193
ADCON1 (A/D Control 1) .........................................
194CCP1CON and CCP2CON (CCP Control) ..............
141CONFIG1H (Configuration Register 1 High) ............
208CONFIG2H (Configuration Register 2 High) ............
209CONFIG2L (Configuration Register 2 Low) .............
208CONFIG4L (Configuration Register 4 Low) .............
209CSEL2 (Chip Select 2) ...............................................
70CSELIO (Chip Select I/O) ..........................................
70INTCON (Interrupt Control) ........................................
91INTCON2 (Interrupt Control 2) ...................................
92INTCON3 (Interrupt Control 3) ...................................
93IPR (Interrupt Priority) ................................................
99LVDCON (LVD Control) ...........................................
204MEMCON (Memory Control) .....................................
63OSCCON (Oscillator Control) ....................................
25PIE (Peripheral Interrupt Enable) ...............................
97PIR (Peripheral Interrupt Request) ............................
95PSPCON (PSP Control) ............................................
50RCON (Register Control) ...........................................
94RCON (RESET Control) .....................................
31RCSTA (Receive Status and Control) .....................
178SSPCON1 (SSP Control 1) .....................................
151SSPCON2 (SSP Control 2) ...................................... 152
SSPSTAT (SSP Status) ..........................................
150STATUS ....................................................................
61STKPTR (Stack Pointer) ...........................................
44T0CON (Timer0 Control) .........................................
127T1CON (Timer1 Control) .........................................
130T2CON (Timer2 Control) .........................................
135T3CON (Timer3 Control) .........................................
137TXSTA (Transmit Status and Control) .....................
177WDTCON (Watchdog Timer Control) ......................
210RESET .............................................................
29Timing Diagram .......................................................
280RETFIE ............................................................................
246RETLW ............................................................................
246RETURN .........................................................................
247Revision History ..............................................................
303RH3:RH0 Pins (I/O Mode) ...............................................
121RH3:RH0 Pins (System Bus Mode) ................................
122RH7:RH4 Pins .................................................................
121RLCF ...............................................................................
247RLNCF ............................................................................
248RRCF ..............................................................................
248RRNCF ............................................................................
249S
Sales and Support ...........................................................
317SCK .................................................................................
153SDI ..................................................................................
153SDO .................................................................................
153Serial Clock, SCK ............................................................
153Serial Data In, SDI ...........................................................
153Serial Data Out, SDO ......................................................
153SETF ...............................................................................
249Slave Select Synchronization ..........................................
156Slave Select, SS ..............................................................
153SLEEP ............................................................
207Software Simulator (MPLAB SIM) ...................................
260Special Features of the CPU ...........................................
207Special Function Register Map .........................................
53Special Function Registers ................................................
49SPI
Associated Registers ...............................................
158Master Mode ...........................................................
155Serial Clock .............................................................
153Serial Data In ...........................................................
153Serial Data Out ........................................................
153Slave Select ............................................................
153SPI Clock .................................................................
155SPI Mode .................................................................
153SPI Module
Slave Mode .............................................................
156Slave Select Synchronization ..................................
156Slave Synch Timing .................................................
156Slave Timing with CKE = 0 ......................................
157Slave Timing with CKE = 1 ......................................
157SS ....................................................................................
153