參數資料
型號： PIC18F45J50T-I/PT
廠商： Microchip Technology
文件頁數： 107/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 32KB 44-TQFP
產品培訓模塊： PIC18 J Series MCU Overview
標準包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設備： 欠壓檢測/復位，DMA，POR，PWM，WDT
輸入/輸出數： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數據轉換器： A/D 13x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
2011 Microchip Technology Inc.
DS39931D-page 47
PIC18F46J50 FAMILY
4.0
LOW-POWER MODES
The PIC18F46J50 family devices can manage power
consumption through clocking to the CPU and the
peripherals. In general, reducing the clock frequency
and number of circuits being clocked reduce power
consumption.
For managing power in an application, the primary
modes of operation are:
Run Mode
Idle Mode
Sleep Mode
Deep Sleep Mode
Additionally, there is an Ultra Low-Power Wake-up
(ULPWU) mode for generating an interrupt-on-change
on RA0.
These modes define which portions of the device are
clocked and at what speed.
The Run and Idle modes can use any of the three
available clock sources (primary, secondary or
internal oscillator blocks).
The Sleep mode does not use a clock source.
The ULPWU mode on RA0 allows a slow falling voltage
to generate an interrupt-on-change on RA0 without
excess current consumption. See Section 4.7 “Ultra
.
The
power-managed
modes
include
several
power-saving features offered on previous PIC
devices, such as clock switching, ULPWU and Sleep
mode. In addition, the PIC18F46J50 family devices add
a new power-managed Deep Sleep mode.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires these
decisions:
Will the CPU be clocked?
If so, which clock source will be used?
The IDLEN bit (OSCCON<7>) controls CPU clocking
and the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
4.1.1
CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
Primary clock source – Defined by the
FOSC<2:0> Configuration bits
Timer1 clock – Provided by the secondary
oscillator
Postscaled internal clock – Derived from the
internal oscillator block
4.1.2
ENTERING POWER-MANAGED
MODES
Switching from one clock source to another begins by
loading the OSCCON register. The SCS<1:0> bits
select the clock source.
Changing these bits causes an immediate switch to the
new clock source, assuming that it is running. The
switch also may be subject to clock transition delays.
These delays are discussed in Section 4.1.3 “Clock
and subsequent
sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many transi-
tions may be done by changing the oscillator select
bits, the IDLEN bit, or the DSEN bit prior to issuing a
SLEEP
instruction.
If the IDLEN and DSEN bits are already configured
correctly, it only may be necessary to perform a SLEEP
instruction to switch to the desired mode.
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