
2002 Microchip Technology Inc.
Preliminary
DS41159B-page 31
PIC18FXX8
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as
’
0
’
,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (
0008h
or
0018h
).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 3-2 for RESET value for specific condition.
5:
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read
’
0
’
.
6:
Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
---- 0000
xxxx xxxx
---- 0000
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0-00 0000
xxxx xxxx
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---- 0000
N/A
N/A
N/A
N/A
N/A
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
0--1 qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---- uuuu
N/A
N/A
N/A
N/A
N/A
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt