
2002 Microchip Technology Inc.
Preliminary
DS41159B-page 337
PIC18FXX8
27.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-5:
EXTERNAL CLOCK TIMING
TABLE 27-6:
EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4
Q1
Q2
Q3
Q4
Q1
1
2
3
3
4
4
Param No.
Symbol
Characteristic
Min
Max
Units
Conditions
1A
F
OSC
External CLKI Frequency
(1)
DC
DC
4
DC
DC
DC
0.1
4
4
5
250
40
100
5
5
250
250
100
40
5
100
30
2.5
10
—
—
—
4
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
MHz
kHz
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
μ
s
ns
ns
ns
XT osc
HS osc
HS + PLL osc
LP osc
EC
RC osc
XT osc
HS osc
HS + PLL osc
LP osc
XT and RC osc
HS osc
HS + PLL osc
LP osc
EC
RC osc
XT osc
HS osc
HS + PLL osc
LP osc
T
CY
= 4/F
OSC
XT osc
LP osc
HS osc
XT osc
LP osc
HS osc
25
10
200
40
4
4
25
10
200
—
—
—
—
—
—
10,000
10,000
100
—
—
—
—
—
20
50
7.5
Oscillator Frequency
(1)
1
T
OSC
External CLKI Period
(1)
Oscillator Period
(1)
2
3
T
CY
TosL,
TosH
Instruction Cycle Time
(1)
External Clock in (OSC1)
High or Low Time
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
Note 1:
Instruction cycle period (T
CY
) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time
limit is "DC" (no clock) for all devices.