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| 型號(hào)： | PIC18F458ESPQTP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN |
| 中文描述： | 高性能，28/40-Pin增強(qiáng)型閃存微控制器和CAN |
| 文件頁(yè)數(shù)： | 228/384頁(yè) |
| 文件大?。?/td> | 3119K |
| 代理商： | PIC18F458ESPQTP |
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PIC18FXX8
DS41159B-page 226
Preliminary
2002 Microchip Technology Inc.
19.5
Message Reception
19.5.1
RECEIVE MESSAGE BUFFERING
The PIC18FXX8 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB), which acts
as a third receive buffer (see Figure 19-4).
19.5.2
RECEIVE BUFFERS
Of the three receive buffers, the MAB is always commit-
ted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception, or
holding a previously received message.
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffers, only
if the acceptance filter criteria are met.
When a message is moved into either of the receive
buffers, the appropriate RXBnIF bit is set. This bit must
be cleared by the MCU when it has completed process-
ing the message in the buffer, in order to allow a new
message to be received into the buffer. This bit pro-
vides a positive lockout to ensure that the MCU has fin-
ished with the message before the PIC18FXX8
attempts to load a new message into the receive buffer.
If the RXBnIE bit is set, an interrupt will be generated to
indicate that a valid message has been received.
19.5.3
RECEIVE PRIORITY
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ-
ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such that if
RXB0 contains a valid message and another valid mes-
sage is received, an overflow error will not occur and
the new message will be moved into RXB1, regardless
of the acceptance criteria of RXB1. There are also two
programmable acceptance filter masks available, one
for each receive buffer (see Section 4.5).
When a message is received, bits <3:0> of the
RXBnCON register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
The RXM bits set special Receive modes. Normally,
these bits are set to ‘
00
’ to enable reception of all valid
messages, as determined by the appropriate accep-
tance filters. In this case, the determination of whether
or not to receive standard or extended messages is
determined by the EXIDE bit in the acceptance filter
register. If the RXM bits are set to ‘
01
’ or ‘
10
’, the
receiver will accept only messages with standard or
extended identifiers, respectively. If an acceptance fil-
ter has the EXIDE bit set, such that it does not corre-
spond with the RXM mode, that acceptance filter is
rendered useless. These two modes of RXM bits can
be used in systems where it is known that only standard
or extended messages will be on the bus. If the RXM
bits are set to ‘
11
’, the buffer will receive all messages,
regardless of the values of the acceptance filters. Also,
if a message has an error before the end of frame, that
portion of the message assembled in the MAB before
the error frame, will be loaded into the buffer. This
mode has some value in debugging a CAN system and
would not be used in an actual system environment.
19.5.4
TIME-STAMPING
The CAN module can be programmed to generate a
time-stamp for every message that is received. When
enabled, the module generates a capture signal for
CCP1, which in turns captures the value of either
Timer1 or Timer3. This value can be used as the
message time-stamp.
To use the time-stamp capability, the CANCAP bit
(CIOCAN<4>) must be set. This replaces the capture
input for CCP1 with the signal generated from the CAN
module. In addition, CCP1CON<3:0> must be set to
‘
0011
’ to enable the CCP special event trigger for CAN
events.
FIGURE 19-4:
RECEIVE BUFFER BLOCK
DIAGRAM
Note:
The entire contents of the MAB are moved
into the receive buffer once a message is
accepted. This means that, regardless of
the type of identifier (standard or extended)
and the number of data bytes received, the
entire receive buffer is overwritten with the
MAB contents. Therefore, the contents of
all registers in the buffer must be assumed
to have been modified when any message
is received.
Acceptance Mask
RXM0
Acceptance Filter
RXF0
Acceptance Filter
RXF1
Message Assembly Buffer
Acceptance Filter
RXM2
Acceptance Filter
RXF3
Acceptance Filter
RXF4
Acceptance Filter
RXF5
Acceptance Mask
RXM1
RXB0
RXB1
Accept
Accept
Data and
Identifier
Identifier
Data and
Identifier
Identifier
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC18F458-I/L | 功能描述:8位微控制器 -MCU 32KB 1536 RAM 34 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F458-I/L | 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU CAN ADC 18F458 |
| PIC18F458-I/P | 功能描述:8位微控制器 -MCU 32KB 1536 RAM 34 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F458-I/P | 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU CAN ADC 18F458 |
| PIC18F458-I/PT | 功能描述:8位微控制器 -MCU 32KB 1536 RAM 34 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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