參數(shù)資料
型號: PIC18F4553
廠商: Microchip Technology Inc.
英文描述: 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology
中文描述: 28/40/44-Pin高性能,增強(qiáng)型閃存,USB微控制器與12位A / D和納瓦技術(shù)
文件頁數(shù): 29/46頁
文件大?。?/td> 607K
代理商: PIC18F4553
2007 Microchip Technology Inc.
Preliminary
DS39887B-page 27
PIC18F2458/2553/4458/4553
2.6
A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘
010
’, and selecting a
4 T
AD
acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
CY
wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 2-4:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> =
000
, T
ACQ
=
0
)
FIGURE 2-5:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> =
010
, T
ACQ
= 4 T
AD
)
Note:
The GO/DONE bit should
NOT
be set in
the same instruction that turns on the A/D.
Code should wait at least 2
μ
s after
enabling the A/D before beginning an
acquisition and conversion cycle.
T
AD
1 T
AD
2 T
AD
3 T
AD
4 T
AD
5 T
AD
6 T
AD
7 T
AD
8
T
AD
11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
T
AD
9 T
AD
10
T
CY
– T
AD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b2
b11
b8
b7
b6
b5
b4
b3
b10
b9
On the following cycle:
Discharge
(typically 200 ns)
T
AD
13
T
AD
12
b0
b1
T
AD
1
1
2
3
4
b9
5
b8
6
b7
7
b6
8
13
b0
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
(Holding capacitor is disconnected)
9
b4
12
b1
Conversion starts
1
2
3
4
T
ACQT
Cycles
T
AD
Cycles
Automatic
Acquisition
Time
b11
b5
b10
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
T
AD
1
Discharge
(typically
200 ns)
10
b3
11
b2
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