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  • 參數(shù)資料
    型號: PIC18F4480-E/ML
    廠商: Microchip Technology
    文件頁數(shù): 36/88頁
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 8KX16 44QFN
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    標準包裝: 45
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 25MHz
    連通性: CAN,I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
    輸入/輸出數(shù): 36
    程序存儲器容量: 16KB(8K x 16)
    程序存儲器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 768 x 8
    電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 44-VQFN 裸露焊盤
    包裝: 管件
    2010 Microchip Technology Inc.
    DS21801F-page 41
    MCP2515
    5.3
    Programming Time Segments
    Some requirements for programming of the time
    segments:
    PropSeg + PS1 >= PS2
    PropSeg + PS1 >= TDELAY
    PS2 > SJW
    For example, assuming that a 125 kHz CAN baud rate
    with FOSC = 20 MHz is desired:
    TOSC = 50 ns, choose BRP<5:0> = 04h, then
    TQ = 500 ns. To obtain 125 kHz, the bit time must be 16
    TQ.
    Typically, the sampling of the bit should take place at
    about 60-70% of the bit time, depending on the system
    parameters. Also, typically, the TDELAY is 1-2 TQ.
    SyncSeg = 1 TQ and PropSeg = 2 TQ. So setting
    PS1 = 7 TQ would place the sample at 10 TQ after the
    transition. This would leave 6 TQ for PS2.
    Since PS2 is 6, according to the rules, SJW could be a
    maximum of 4 TQ. However, a large SJW is typically
    only necessary when the clock generation of the differ-
    ent nodes is inaccurate or unstable, such as using
    ceramic resonators. So a SJW of 1 is usually enough.
    5.4
    Oscillator Tolerance
    The bit timing requirements allow ceramic resonators
    to be used in applications with transmission rates of up
    to 125 kbit/sec as a rule of thumb. For the full bus
    speed range of the CAN protocol, a quartz oscillator is
    required. A maximum node-to-node oscillator variation
    of 1.7% is allowed.
    5.5
    Bit Timing Configuration
    Registers
    The configuration registers (CNF1, CNF2, CNF3)
    control the bit timing for the CAN bus interface. These
    registers can only be modified when the MCP2515 is in
    Configuration mode (see Section 10.0 “Modes of
    5.5.1
    CNF1
    The BRP<5:0> bits control the baud rate prescaler.
    These bits set the length of TQ relative to the OSC1
    input frequency, with the minimum TQ length being
    2TOSC
    (when
    BRP<5:0>
    =
    ‘b000000’).
    The
    SJW<1:0> bits select the SJW in terms of number of
    TQs.
    5.5.2
    CNF2
    The PRSEG<2:0> bits set the length (in TQ’s) of the
    propagation segment. The PHSEG1<2:0> bits set the
    length (in TQ’s) of PS1.
    The SAM bit controls how many times the RXCAN pin
    is sampled. Setting this bit to a ‘1’ causes the bus to be
    sampled three times: twice at TQ/2 before the sample
    point and once at the normal sample point (which is at
    the end of PS1). The value of the bus is determined to
    be the majority sampled. If the SAM bit is set to a ‘0’,
    the RXCAN pin is sampled only once at the sample
    point.
    The BTLMODE bit controls how the length of PS2 is
    determined. If this bit is set to a ‘1’, the length of PS2 is
    determined by the PHSEG2<2:0> bits of CNF3 (see
    Section 5.5.3 “CNF3”). If the BTLMODE bit is set to a
    ‘0’, the length of PS2 is greater than that of PS1 and the
    information processing time (which is fixed at 2 TQ for
    the MCP2515).
    5.5.3
    CNF3
    The PHSEG2<2:0> bits set the length (in TQ’s) of PS2,
    if the CNF2.BTLMODE bit is set to a ‘1’. If the
    BTLMODE bit is set to a ‘0’, the PHSEG2<2:0> bits
    have no effect.
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