參數(shù)資料
型號(hào): PIC18F442T-I/PT
廠商: Microchip Technology
文件頁數(shù): 17/134頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8KX16 EE A/D 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 帶卷 (TR)
1997 Microchip Technology Inc.
DS30444E - page 113
PIC16C9XX
14.5
Interrupts
The PIC16C9XX family has up to 9 sources of interrupt:
The interrupt control register (INTCON) records individ-
ual interrupt requests in ag bits. It also has individual
and global interrupt enable bits.
Interrupt Sources
Applicable
Devices
External interrupt RB0/INT
923
924
TMR0 overow interrupt
923
924
PORTB change interrupts
(pins RB7:RB4)
923
924
A/D Interrupt
923
924
TMR1 overow interrupt
923
924
TMR2 matches period interrupt
923
924
CCP1 interrupt
923
924
Synchronous serial port interrupt
923
924
LCD Module interrupt
923
924
Note:
Individual interrupt ag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s ag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in various
registers. Individual interrupt bits are set regardless of
the status of the GIE bit. The GIE bit is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overow interrupt ags are contained in
the INTCON register.
The peripheral interrupt ags are contained in the spe-
cial function register PIR1. The corresponding interrupt
enable bits are contained in special function register
PIE1, and the peripheral interrupt enable bit is con-
tained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt ag bits. The interrupt ag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin
or RB Port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends
when
the
interrupt
event
occurs
(Figure 14-15). The latency is the same for one or two
cycle instructions. Individual interrupt ag bits are set
regardless of the status of their corresponding mask bit
or the GIE bit.
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