參數(shù)資料
型號: PIC18F442-I/PT
廠商: Microchip Technology
文件頁數(shù): 104/134頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8KX16 EE A/D 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
1997 Microchip Technology Inc.
DS30444E - page 71
PIC16C9XX
Figure 11-13 and Figure 11-14 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identical
to the start condition (SDA goes high-to-low while SCL
is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to
send “commands” to the slave and then receive the
requested information or to address a different slave
device. This sequence is shown in Figure 11-15.
FIGURE 11-13: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-14: MASTER-RECEIVER SEQUENCE
FIGURE 11-15: COMBINED FORMAT
For 7-bit address:
S
Slave Address
First 7 bits
S
R/W A1 Slave Address
Second byte
A2
Data A
Data
P
A master transmitter addresses a slave receiver
with a 10-bit address.
A/A
Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
For 7-bit address:
S
Slave Address
First 7 bits
S
R/W A1 Slave Address
Second byte
A2
A master transmitter addresses a slave receiver
with a 10-bit address.
Slave Address R/W A Data A Data A
P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the rst byte.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
Slave Address
First 7 bits
Sr
R/W A3
A
Data A
P
Data
(read)
Combined format:
S
Combined format - A master addresses a slave with a 10-bit address, then transmits
Slave Address R/W A Data A/A Sr
P
(read)
Sr = repeated
Transfer direction of data and acknowledgment bits depends on R/W bits.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Slave Address
First 7 bits
Sr
R/W A
(write)
data to this slave and reads data from this slave.
Slave Address
Second byte
Data
Sr Slave Address
First 7 bits
R/W A Data A
A P
A
Data A/A
Data
(read)
Slave Address R/W A Data A/A
Start Condition
(write)
Direction of transfer
may change at this point
(read or write)
(n bytes + acknowledge)
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