THLD
鍙冩暩璩囨枡
鍨嬭櫉锛� PIC18F43K20-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩锛� 33/42闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC PIC MCU FLASH 4KX16 40-DIP
鐢㈠搧鍩硅〒妯″锛� XLP Deep Sleep Mode
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鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
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EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 3.6 V
鏁告摎杞夋彌鍣細 A/D 14x10b
鎸暕鍣ㄥ瀷锛� 鍏ч儴
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灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
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鐢㈠搧鐩寗闋侀潰锛� 655 (CN2011-ZH PDF)
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 39
PIC18F2XK20/4XK20
P12
THLD2
Input Data Hold Time from MCLR/VPP/RE3
鈫�
2鈥�
渭s
P13
TSET2VDD
鈫� Setup Time to MCLR/VPP/RE3 鈫�
100
鈥�
ns
P14
TVALID
Data Out Valid from PGC
鈫�
10
鈥�
ns
P15
TSET3PGM
鈫� Setup Time to MCLR/VPP/RE3 鈫�
2鈥�
渭s
P16
TDLY8
Delay between Last PGC
鈫� and MCLR/VPP/RE3 鈫�
0鈥�
s
P17
THLD3MCLR/VPP/RE3
鈫� to VDD 鈫�
鈥�
100
ns
P18
THLD4MCLR/VPP/RE3
鈫� to PGM 鈫�
0鈥�
s
P19
THIZ
Delay from PGC
鈫� to PGD High-Z
3
10
nS
P20
TPPDP
Hold time after VPP changes
5
鈥�
渭s
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25
掳C is recommended
Param
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1:
Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only)
+ 1.5
渭s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and
TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data
sheet for the particular device.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
PIC16C58B-40/P IC MCU OTP 2KX12 18DIP
1408339-7 CONN JACK QMA BULKHD RG-58/141
PIC16LC58B-04I/P IC MCU OTP 2KX12 18DIP
1408339-5 CONN JACK QMA BULKHD RG-142/223
1408339-3 CONN JACK QMA BULKHEAD RG-316
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