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dsPIC33F
DS70165E-page 228
Preliminary
2007 Microchip Technology Inc.
REGISTER 19-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0 HC
R/W-0
R-0
R-1
UTXISEL1
UTXINV(1)
UTXISEL0
鈥�
UTXBRK
UTXEN
UTXBF
TRMT
bit 15
bit 8
R/W-0
R-1
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11
=Reserved; do not use
10
=Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01
=Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00
=Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)
1
= IrDA encoded, UxTX Idle state is 鈥�1鈥�
0
= IrDA encoded, UxTX Idle state is 鈥�0鈥�
bit 12
Unimplemented: Read as 鈥�0鈥�
bit 11
UTXBRK: Transmit Break bit
1
= Send Sync Break on next transmission 鈥� Start bit, followed by twelve 鈥�0鈥� bits, followed by Stop bit;
cleared by hardware upon completion
0
= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit
1
= Transmit enabled, UxTX pin controlled by UARTx
0
= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1
= Transmit buffer is full
0
= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1
= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11
=Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10
=Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x
=Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1
= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0
= Address Detect mode disabled
Note 1:
Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
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