• 參數(shù)資料
    型號(hào): PIC18F4221-I/P
    廠商: Microchip Technology
    文件頁(yè)數(shù): 41/110頁(yè)
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 2KX16 400IP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 10
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 40MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
    輸入/輸出數(shù): 36
    程序存儲(chǔ)器容量: 4KB(2K x 16)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 512 x 8
    電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 40-DIP(0.600",15.24mm)
    包裝: 管件
    產(chǎn)品目錄頁(yè)面: 642 (CN2011-ZH PDF)
    配用: DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
    444-1001-ND - DEMO BOARD FOR PICMICRO MCU
    ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
    PIC18F2221/2321/4221/4321 FAMILY
    DS39689F-page 36
    2009 Microchip Technology Inc.
    3.7.1
    OSCILLATOR CONTROL REGISTER
    The OSCCON register (Register 3-2) controls several
    aspects of the device clock’s operation, both in full
    power operation and in power-managed modes.
    The System Clock Select bits, SCS<1:0>, select the
    clock source. The available clock sources are the
    primary clock (defined by the FOSC<3:0> Configura-
    tion bits), the secondary clock (Timer1 oscillator) and
    the internal oscillator block. The clock source changes
    immediately after either of the SCS<1:0> bits are
    changed, following a brief clock transition interval. The
    SCS bits are reset on all forms of Reset.
    The
    Internal
    Oscillator
    Frequency
    Select
    bits
    (IRCF<2:0>) select the frequency output of the internal
    oscillator block to drive the device clock. The choices
    are the INTRC source (31 kHz), the INTOSC source
    (8 MHz) or one of the frequencies derived from the
    INTOSC postscaler (31.25 kHz to 4 MHz). If the
    internal oscillator block is supplying the device clock,
    changing the states of these bits will have an immedi-
    ate change on the internal oscillator’s output. On
    device Resets, the default output frequency of the
    internal oscillator block is set at 1 MHz.
    When a nominal output frequency of 31 kHz is selected
    (IRCF<2:0> = 000), users may choose which internal
    oscillator acts as the source. This is done with the
    INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
    Setting this bit selects INTOSC as a 31.25 kHz clock
    source derived from the INTOSC postscaler. Clearing
    INTSRC selects INTRC (nominally 31 kHz) as the
    clock source and disables the INTOSC to reduce
    current consumption.
    This option allows users to select the tunable and more
    precise INTOSC as a clock source, while maintaining
    power savings with a very low clock speed. Addition-
    ally, the INTOSC source will already be stable should a
    switch to a higher frequency be needed quickly.
    Regardless of the setting of INTSRC, INTRC always
    remains the clock source for features such as the
    Watchdog Timer and the Fail-Safe Clock Monitor.
    The OSTS, IOFS and T1RUN bits indicate which clock
    source is currently providing the device clock. The
    OSTS bit indicates that the Oscillator Start-up Timer
    and PLL Start-up Timer (if enabled) have timed out and
    the primary clock is providing the device clock in
    primary clock modes. The IOFS bit indicates when the
    internal oscillator block has stabilized and is providing
    the device clock in RC Clock modes. The T1RUN bit
    (T1CON<6>) indicates when the Timer1 oscillator is
    providing the device clock in secondary clock modes.
    In power-managed modes, only one of these three bits
    will be set at any time. If none of these bits are set, the
    INTRC is providing the clock or the internal oscillator
    block has just started and is not yet stable.
    The IDLEN bit controls whether the device goes into
    Sleep mode or one of the Idle modes when the SLEEP
    instruction is executed.
    The use of the flag and control bits in the OSCCON
    register is discussed in more detail in Section 4.0
    3.7.2
    OSCILLATOR TRANSITIONS
    The PIC18F2221/2321/4221/4321 family of devices con-
    tains circuitry to prevent clock “glitches” when switching
    between clock sources. A short pause in the device clock
    occurs during the clock switch. The length of this pause
    is the sum of two cycles of the old clock source and three
    to four cycles of the new clock source. This formula
    assumes that the new clock source is stable.
    Clock transitions are discussed in greater detail in
    Note 1: The Timer1 oscillator must be enabled to
    select the secondary clock source. The
    Timer1 oscillator is enabled by setting the
    T1OSCEN bit in the Timer1 Control regis-
    ter (T1CON<3>). If the Timer1 oscillator
    is not enabled, then any attempt to select
    a secondary clock source will be ignored.
    2: It is recommended that the Timer1
    oscillator be operating and stable before
    selecting the secondary clock source or a
    very long delay may occur while the
    Timer1 oscillator starts.
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