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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC18F26K22-E/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 14/71闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 64KB FLASH 28SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 64KB锛�32K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 1K x 8 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 19x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�鐣�(d膩ng)鍓嶇14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�
2010-2012 Microchip Technology Inc.
DS41412F-page 21
PIC18(L)F2X/4XK22
20
17
VDD
P
鈥�
Positive supply for logic and I/O pins.
8, 19
5, 16
VSS
P
鈥�
Ground reference for logic and I/O pins.
TABLE 1-2:
PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP,
SOIC
QFN,
UQFN
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
TABLE 1-3:
PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP
TQFP
QFN
UQFN
219
19
17
RA0/C12IN0-/AN0
RA0
I/O
TTL
Digital I/O.
C12IN0-
I
Analog Comparators C1 and C2 inverting input.
AN0
I
Analog Analog input 0.
320
20
18
RA1/C12IN1-/AN1
RA1
I/O
TTL
Digital I/O.
C12IN1-
I
Analog Comparators C1 and C2 inverting input.
AN1
I
Analog Analog input 1.
421
21
19
RA2/C2IN+/AN2/DACOUT/VREF-
RA2
I/O
TTL
Digital I/O.
C2IN+
I
Analog Comparator C2 non-inverting input.
AN2
I
Analog Analog input 2.
DACOUT
O
Analog DAC Reference output.
VREF-
I
Analog A/D reference voltage (low) input.
522
22
20
RA3/C1IN+/AN3/VREF+
RA3
I/O
TTL
Digital I/O.
C1IN+
I
Analog Comparator C1 non-inverting input.
AN3
I
Analog Analog input 3.
VREF+
I
Analog A/D reference voltage (high) input.
623
23
21
RA4/C1OUT/SRQ/T0CKI
RA4
I/O
ST
Digital I/O.
C1OUT
O
CMOS
Comparator C1 output.
SRQ
O
TTL
SR latch Q output.
T0CKI
I
ST
Timer0 external clock input.
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
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