
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 31
PIC18F2XK20/4XK20
WDTEN
CONFIG2H
Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled (control is placed on SWDTEN bit)
MCLRE
CONFIG3H
MCLR Pin Enable bit
1
=MCLR pin enabled, RE3 input pin disabled
0
= RE3 input pin enabled, MCLR pin disabled
HFOFST
CONFIG3H
HFINTOSC Fast Start
1
= HFINTOSC output is not delayed
0
= HFINTOSC output is delayed until oscillator is stable (IOFS = 1)
LPT1OSC
CONFIG3H
Low-Power Timer1 Oscillator Enable bit
1
= Timer1 configured for low-power operation
0
= Timer1 configured for higher power operation
PBADEN
CONFIG3H
PORTB A/D Enable bit
1
= PORTB A/D<4:0> pins are configured as analog input channels on Reset
0
= PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2MX
CONFIG3H
CCP2 MUX bit
1
= CCP2 input/output is multiplexed with RC1
0
= CCP2 input/output is multiplexed with RB3
DEBUG
CONFIG4L
Background Debugger Enable bit
1
= Background debugger disabled, RB6 and RB7 configured as general
purpose I/O pins
0
= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit
Debug
XINST
CONFIG4L
Extended Instruction Set Enable bit
1
= Instruction set extension and Indexed Addressing mode enabled
0
= Instruction set extension and Indexed Addressing mode disabled
(Legacy mode)
LVP
CONFIG4L
Low-Voltage Programming Enable bit
1
= Low-Voltage Programming enabled, RB5 is the PGM pin
0
= Low-Voltage Programming disabled, RB5 is an I/O pin
STVREN
CONFIG4L
Stack Overflow/Underflow Reset Enable bit
1
= Reset on stack overflow/underflow enabled
0
= Reset on stack overflow/underflow disabled
TABLE 5-3:
PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
.