參數(shù)資料
型號: PIC18F26K20-I/SO
廠商: Microchip Technology
文件頁數(shù): 42/42頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32KX16 28-SOIC
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
AC164303-ND - MODULE SKT FOR PM3 64TQFP
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 9
PIC18F2XK20/4XK20
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through table reads and table
writes. Their locations in the memory map are shown in
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-
tion Word”. These Configuration bits read out
normally, even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These device ID bits read out normally, even
after code protection.
2.3.1
MEMORY ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three Pointer registers:
TBLPTRU, at RAM address 0FF8h
TBLPTRH, at RAM address 0FF7h
TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using any read or write
operations.
FIGURE 2-10:
CONFIGURATION AND ID LOCATIONS FOR PIC18F2XK20/4XK20 DEVICES
TBLPTRU
TBLPTRH
TBLPTRL
Addr[21:16]
Addr[15:8]
Addr[7:0]
ID Location 1
200000h
ID Location 2
200001h
ID Location 3
200002h
ID Location 4
200003h
ID Location 5
200004h
ID Location 6
200005h
ID Location 7
200006h
ID Location 8
200007h
CONFIG1L
300000h
CONFIG1H
300001h
CONFIG2L
300002h
CONFIG2H
300003h
CONFIG3L
300004h
CONFIG3H
300005h
CONFIG4L
300006h
CONFIG4H
300007h
CONFIG5L
300008h
CONFIG5H
300009h
CONFIG6L
30000Ah
CONFIG6H
30000Bh
CONFIG7L
30000Ch
CONFIG7H
30000Dh
Device ID1
3FFFFEh
Device ID2
3FFFFFh
Note:
Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
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