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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC18F25K22T-I/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 14/71闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | MCU 8BIT 32KB FLASH 28SSOP |
| 妯欐簴鍖呰锛� | 2,100 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 64MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 1.5K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 | A/D 19x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏ч儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 甯跺嵎 (TR) |
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2010-2012 Microchip Technology Inc.
DS41412F-page 21
PIC18(L)F2X/4XK22
20
17
VDD
P
鈥�
Positive supply for logic and I/O pins.
8, 19
5, 16
VSS
P
鈥�
Ground reference for logic and I/O pins.
TABLE 1-2:
PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP,
SOIC
QFN,
UQFN
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
TABLE 1-3:
PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP
TQFP
QFN
UQFN
219
19
17
RA0/C12IN0-/AN0
RA0
I/O
TTL
Digital I/O.
C12IN0-
I
Analog Comparators C1 and C2 inverting input.
AN0
I
Analog Analog input 0.
320
20
18
RA1/C12IN1-/AN1
RA1
I/O
TTL
Digital I/O.
C12IN1-
I
Analog Comparators C1 and C2 inverting input.
AN1
I
Analog Analog input 1.
421
21
19
RA2/C2IN+/AN2/DACOUT/VREF-
RA2
I/O
TTL
Digital I/O.
C2IN+
I
Analog Comparator C2 non-inverting input.
AN2
I
Analog Analog input 2.
DACOUT
O
Analog DAC Reference output.
VREF-
I
Analog A/D reference voltage (low) input.
522
22
20
RA3/C1IN+/AN3/VREF+
RA3
I/O
TTL
Digital I/O.
C1IN+
I
Analog Comparator C1 non-inverting input.
AN3
I
Analog Analog input 3.
VREF+
I
Analog A/D reference voltage (high) input.
623
23
21
RA4/C1OUT/SRQ/T0CKI
RA4
I/O
ST
Digital I/O.
C1OUT
O
CMOS
Comparator C1 output.
SRQ
O
TTL
SR latch Q output.
T0CKI
I
ST
Timer0 external clock input.
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
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| PIC18F25K50-E/SS | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:32 KB FLASH, 2048 BYTES RAM, 48 MHZ INT. OSC, 25 I/0, PIC18 - Rail/Tube 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:IC MCU 8BIT 32KB FLASH 28SSOP 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:32 KB Flash, 2048 bytes RAM, 48 MHz Int. Osc, 25 I/0, PIC18 Core, USB 2.0, 28 SS |
| PIC18F25K50-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32 KB Flash RAM 48 MHz Int. RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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