參數(shù)資料
型號： PIC18F25K22-E/SP
廠商： Microchip Technology
文件頁數(shù)： 64/71頁
文件大?。?/td> 0K
描述： MCU 8BIT 32KB FLASH 28SDIP
標準包裝： 15
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 24
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 19x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
2010-2012 Microchip Technology Inc.
DS41412F-page 67
PIC18(L)F2X/4XK22
4.7
Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used by software to determine the
nature of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. The table identifies
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear,
WDT
Resets,
STKFUL,
STKUNF,
etc.).
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition
Program
Counter
RCON Register
STKPTR Register
SBOREN
RI
TO
PD
POR BOR
STKFUL
STKUNF
Power-on Reset
0000h
1
111
00
0
RESET
Instruction
0000h
u(2)
0uu
uu
u
Brown-out Reset
0000h
u(2)
111
u0
u
MCLR during Power-Managed
Run Modes
0000h
u(2)
u1u
uu
u
MCLR during Power-Managed
Idle Modes and Sleep Mode
0000h
u(2)
u10
uu
u
WDT Time-out during Full Power
or Power-Managed Run Mode
0000h
u(2)
u0u
uu
u
MCLR during Full Power
Execution
0000h
u(2)
uuu
uu
u
Stack Full Reset (STVREN = 1)
0000h
u(2)
uuu
uu
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u(2)
uuu
uu
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u(2)
uuu
uu
u
1
WDT Time-out during Power-
Managed Idle or Sleep Modes
PC + 2
u(2)
u00
uu
u
Interrupt Exit from Power-
Managed Modes
PC + 2(1)
u(2)
uu0
uu
u
Legend: u = unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2:
Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
TABLE 4-4:
REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RCON
IPEN
SBOREN
—RI
TO
PD
POR
BOR
STKPTR
STKFUL
STKUNF
—
STKPTR<4:0>
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.
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