參數(shù)資料
型號： PIC18F25K20-I/SP
廠商： Microchip Technology
文件頁數(shù)： 5/42頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 16KX16 28-DIP
產(chǎn)品培訓模塊： PIC18 K-Series
XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標準包裝： 15
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 24
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 656 (CN2011-ZH PDF)
配用： AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 13
PIC18F2XK20/4XK20
3.0
DEVICE PROGRAMMING
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program or erase.
3.1
ICSP Erase
3.1.1
HIGH-VOLTAGE ICSP BULK ERASE
Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h and 3C0005h. Code memory may be erased
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block erased. Erase options are detailed in
If
data
EEPROM
is
code-protected
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1:
BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
The code sequence to erase the entire device is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.
TABLE 3-2:
BULK ERASE COMMAND
SEQUENCE
FIGURE 3-1:
BULK ERASE FLOW
Description
Data
(3C0005h:3C0004h)
Chip Erase
0F8Fh
Erase User ID
0088h
Erase Data EEPROM
0084h
Erase Boot Block
0081h
Erase Config Bits
0082h
Erase Code EEPROM Block 0
0180h
Erase Code EEPROM Block 1
0280h
Erase Code EEPROM Block 2
0480h
Erase Code EEPROM Block 3
0880h
Note:
A Bulk Erase is the only way to reprogram
code-protect bits from an “on” state to an
“off” state.
4-Bit
Command
Data
Payload
Core Instruction
0000
0E 3C
MOVLW 3Ch
0000
6E F8
MOVWF TBLPTRU
0000
0E 00
MOVLW 00h
0000
6E F7
MOVWF TBLPTRH
0000
0E 05
MOVLW 05h
0000
6E F6
MOVWF TBLPTRL
1100
0F 0F
Write 0Fh to 3C0005h
0000
0E 3C
MOVLW 3Ch
0000
6E F8
MOVWF TBLPTRU
0000
0E 00
MOVLW 00h
0000
6E F7
MOVWF TBLPTRH
0000
0E 04
MOVLW 04h
0000
6E F6
MOVWF TBLPTRL
1100
8F 8F
Write 8F8Fh TO 3C0004h
to erase entire device.
0000
00 00
NOP
0000
00 00
Hold PGD low until erase
completes.
Start
Done
Write 8F8Fh to
3C0004h to Erase
Entire Device
Write 0F0Fh
Delay P11 + P10
Time
to 3C0005h
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