參數(shù)資料
型號: PIC18F252T-E/SO
廠商: Microchip Technology
文件頁數(shù): 89/134頁
文件大?。?/td> 0K
描述: IC MCU CMOS 40MHZ 16K FLSH28SOIC
標準包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC16C9XX
DS30444E - page 58
1997 Microchip Technology Inc.
10.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 10-2). An event is dened as:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request ag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1
CCP PIN CONFIGURATION
In capture mode, the RC2/CCP1 pin should be cong-
ured as an input by setting the TRISC<2> bit.
FIGURE 10-2: CAPTURE MODE OPERATION
BLOCK DIAGRAM
10.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode the capture
operation may not work.
10.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep
enable bit CCP1IE (PIE1<2>) clear to avoid false inter-
rupts and should clear ag bit CCP1IF following any
such change in operating mode.
10.1.4
CCP PRESCALER
There are four prescaler settings, specied by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Note:
If the RC2/CCP1 pin is congured as an
output, a write to the port can cause a cap-
ture condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set CCP1IF
PIR1<2>
Capture
Enable
Q’s
CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
pin
CCP
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the rst capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture prescal-
ers. This example also clears the prescaler counter and
will not generate the “false” interrupt.
EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON
; Turn CCP module off
MOVLW
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with
; this value
10.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Driven High
Driven Low
Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, a compare interrupt is also generated.
FIGURE 10-3: COMPARE MODE
OPERATION BLOCK DIAGRAM
10.2.1
CCP PIN CONFIGURATION
The user must congure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Special event trigger will reset Timer1, but not
T
rigger
Set CCP1IF
PIR1<2>
match
RC2/CCP1
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
set interrupt ag bit TMR1IF (PIR1<0>).
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