參數(shù)資料
型號: PIC18F2420-E/ML
廠商: Microchip Technology
文件頁數(shù): 82/151頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28QFN
產(chǎn)品培訓模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
標準包裝: 61
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 349
PIC16(L)F1782/3
29.0 INSTRUCTION SET SUMMARY
Each instruction is a 14-bit word containing the opera-
tion code (opcode) and all required operands. The
opcodes are broken into three broad categories.
Byte Oriented
Bit Oriented
Literal and Control
The literal and control category contains the most var-
ied instruction word format.
Table 29-3 lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
Subroutine takes two cycles (CALL, CALLW)
Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
29.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 29-1:
OPCODE FIELD
DESCRIPTIONS
TABLE 29-2:
ABBREVIATION
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
Field
Description
PC
Program Counter
TO
Time-out bit
C
Carry bit
DC
Digit carry bit
Z
Zero bit
PD
Power-down bit
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