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參數(shù)資料
| 型號： | PIC18F23K20-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 4KX16 28-SSOP |
| 產品培訓模塊： | XLP Deep Sleep Mode 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 47 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 64MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 11x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 產品目錄頁面： | 655 (CN2011-ZH PDF) |
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2009 Microchip Technology Inc.
Advance Information
DS41297F-page 11
PIC18F2XK20/4XK20
2.6
Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
When the LVP Configuration bit is ‘1’ (see Section 5.3
the
Low-
Voltage ICSP mode is enabled. As shown in Figure 2-14,
Low-Voltage ICSP Program/Verify mode is entered by
holding PGC and PGD low, placing a logic high on PGM
and then raising MCLR/VPP/RE3 to VIH. In this mode, the
RB5/PGM pin is dedicated to the programming function
and ceases to be a general purpose I/O pin. Figure 2-15
shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-14:
ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
FIGURE 2-15:
EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
2.7
Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
2.7.1
4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-7. The 4-bit com-
mand is shown Most Significant bit (MSb) first. The
command operand, or “Data Payload”, is shown
<MSB><LSB>. Figure 2-16 demonstrates how to
serially present a 20-bit command/operand to the
device.
2.7.2
CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 2-6:
COMMANDS FOR
PROGRAMMING
MCLR/VPP/RE3
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
PGM
P18
VDD
VIH
Description
4-Bit
Command
Core Instruction
(Shift in16-bit instruction)
0000
Shift out TABLAT register
0010
Table Read
1000
Table Read, post-increment
1001
Table Read, post-decrement
1010
Table Read, pre-increment
1011
Table Write
1100
Table Write, post-increment by 2
1101
Table Write, start programming,
post-increment by 2
1110
Table Write, start programming
1111
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