參數(shù)資料
型號(hào)： PIC18F2321T-I/ML
廠商： Microchip Technology
文件頁(yè)數(shù)： 77/110頁(yè)
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 4KX16 28QFN
標(biāo)準(zhǔn)包裝： 1,600
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 25
程序存儲(chǔ)器容量： 8KB（4K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 帶卷 (TR)
2009 Microchip Technology Inc.
DS39689F-page 69
PIC18F2221/2321/4221/4321 FAMILY
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
STKPTR
STKFUL(6)
STKUNF(6)
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
PCLATU
—
Holding Register for PC<21:16>
--00 0000
PCLATH
Holding Register for PC<15:8>
0000 0000
PCL
PC Low Byte (PC<7:0>)
0000 0000
TBLPTRU
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
PRODH
Product Register High Byte
xxxx xxxx
PRODL
Product Register Low Byte
xxxx xxxx
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—TMR0IP
—RBIP
1111 -1-1
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
BSR
—
Bank Select Register
---- 0000
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
FSR2H
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
STATUS
—
—N
OV
Z
DC
C
---x xxxx
Legend:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note
1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
2:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3:
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
4:
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
5:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6:
Bit 7 and bit 6 are cleared by user software or by a POR.
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