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    參數(shù)資料
    型號: PIC18F2221T-I/ML
    廠商: Microchip Technology
    文件頁數(shù): 50/110頁
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 2KX16 28QFN
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    標準包裝: 1,600
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 40MHz
    連通性: I²C,SPI,UART/USART
    外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
    輸入/輸出數(shù): 25
    程序存儲器容量: 4KB(2K x 16)
    程序存儲器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 512 x 8
    電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-VQFN 裸露焊盤
    包裝: 帶卷 (TR)
    PIC18F2221/2321/4221/4321 FAMILY
    DS39689F-page 44
    2009 Microchip Technology Inc.
    4.4.1
    PRI_IDLE MODE
    This mode is unique among the three low-power Idle
    modes, in that it does not disable the primary device
    clock. For timing sensitive applications, this allows for
    the fastest resumption of device operation with its more
    accurate primary clock source, since the clock source
    does not have to “warm-up” or transition from another
    oscillator.
    PRI_IDLE mode is entered from PRI_RUN mode by
    setting the IDLEN bit and executing a SLEEP instruc-
    tion. If the device is in another Run mode, set IDLEN
    first, then clear the SCS bits and execute SLEEP.
    Although the CPU is disabled, the peripherals continue
    to be clocked from the primary clock source specified
    by the FOSC<3:0> Configuration bits. The OSTS bit
    remains set (see Figure 4-7).
    When a wake event occurs, the CPU is clocked from the
    primary clock source. A delay of interval TCSD (parame-
    ter 38, Table 27-10) is required between the wake event
    and when code execution starts. This is required to
    allow the CPU to become ready to execute instructions.
    After the wake-up, the OSTS bit remains set. The
    IDLEN and SCS bits are not affected by the wake-up
    4.4.2
    SEC_IDLE MODE
    In SEC_IDLE mode, the CPU is disabled but the
    peripherals continue to be clocked from the Timer1
    oscillator. This mode is entered from SEC_RUN by
    setting the IDLEN bit and executing a SLEEP
    instruction. If the device is in another Run mode, set the
    IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and
    execute SLEEP. When the clock source is switched to
    the Timer1 oscillator, the primary oscillator is shut down,
    the OSTS bit is cleared and the T1RUN bit is set.
    When a wake event occurs, the peripherals continue to
    be clocked from the Timer1 oscillator. After an interval
    of TCSD following the wake event, the CPU begins exe-
    cuting code being clocked by the Timer1 oscillator. The
    IDLEN and SCS bits are not affected by the wake-up;
    the Timer1 oscillator continues to run (see Figure 4-8).
    FIGURE 4-7:
    TRANSITION TIMING FOR ENTRY TO IDLE MODE
    FIGURE 4-8:
    TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
    Note:
    The Timer1 oscillator should already be
    running prior to entering SEC_IDLE mode.
    If the T1OSCEN bit is not set when writing
    the SCS<1:0> bits, entry to SEC_IDLE
    mode will not occur. If the Timer1 oscillator
    is enabled but not yet running, peripheral
    clocks will be delayed until the oscillator
    has started. In such situations, initial oscil-
    lator operation is far from stable and
    unpredictable operation may result.
    Q1
    Peripheral
    Program
    PC
    PC + 2
    OSC1
    Q3
    Q4
    Q1
    CPU Clock
    Clock
    Counter
    Q2
    OSC1
    Peripheral
    Program
    PC
    CPU Clock
    Q1
    Q3
    Q4
    Clock
    Counter
    Q2
    Wake Event
    TCSD
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