參數(shù)資料
型號(hào): PIC18F1330T-I/ML
廠商: Microchip Technology
文件頁(yè)數(shù): 182/318頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28QFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 8KB(4K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤(pán)
包裝: 帶卷 (TR)
其它名稱(chēng): PIC18F1330T-I/MLTR
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PIC18F1230/1330
DS39758D-page 262
2009 Microchip Technology Inc.
22.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 6.5.1
). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (‘a(chǎn)’ = 0) or in a
GPR bank designated by the BSR (‘a(chǎn)’ = 1). When the
extended instruction set is enabled and ‘a(chǎn)’ = 0,
however, a file register argument of 5Fh or less is
interpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and bit-
oriented instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended
instruction
set
(see
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing mode.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
22.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing mode, the Access RAM
argument is never specified; it will automatically be
assumed to be ‘0’. This is in contrast to standard
operation (extended instruction set disabled) when ‘a(chǎn)’
is set on the basis of the target address. Declaring the
Access RAM bit in this mode will also generate an error
in the MPASM Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
22.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F1230/1330,
it is very important to consider the type of code. A large,
re-entrant application that is written in ‘C’ and would
benefit from efficient compilation will do well when
using
the
instruction
set
extensions.
Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
Note:
Enabling
the
PIC18
instruction
set
extension may cause legacy applications
to behave erratically or fail entirely.
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