參數(shù)資料
型號: PIC17LC752T-08I/PT
廠商: Microchip Technology
文件頁數(shù): 105/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 8KX16 A/D 64TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: OTP
RAM 容量: 678 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
其它名稱: PIC17LC752T-08IPT
2000 Microchip Technology Inc.
DS30289B-page 49
PIC17C7XX
Bank 2
10h
TMR1
Timer1’s Register
xxxx xxxx
uuuu uuuu
11h
TMR2
Timer2’s Register
xxxx xxxx
uuuu uuuu
12h
TMR3L
Timer3’s Register; Low Byte
xxxx xxxx
uuuu uuuu
13h
TMR3H
Timer3’s Register; High Byte
xxxx xxxx
uuuu uuuu
14h
PR1
Timer1’s Period Register
xxxx xxxx
uuuu uuuu
15h
PR2
Timer2’s Period Register
xxxx xxxx
uuuu uuuu
16h
PR3L/CA1L
Timer3’s Period Register - Low Byte/Capture1 Register; Low Byte
xxxx xxxx
uuuu uuuu
17h
PR3H/CA1H
Timer3’s Period Register - High Byte/Capture1 Register; High Byte
xxxx xxxx
uuuu uuuu
Bank 3
10h
PW1DCL
DC1
DC0
xx-- ----
uu-- ----
11h
PW2DCL
DC1
DC0
TM2PW2
xx0- ----
uu0- ----
12h
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
14h
CA2L
Capture2 Low Byte
xxxx xxxx
uuuu uuuu
15h
CA2H
Capture2 High Byte
xxxx xxxx
uuuu uuuu
16h
TCON1
CA2ED1
CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS
TMR1CS
0000 0000
17h
TCON2
CA2OVF
CA1OVF
PWM2ON
PWM1ON
CA1/PR3
TMR3ON
TMR2ON
TMR1ON
0000 0000
Bank 4
10h
PIR2
SSPIF
BCLIF
ADIF
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
11h
PIE2
SSPIE
BCLIE
ADIE
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
12h
Unimplemented
---- ----
13h
RCSTA2
SPEN
RX9
SREN
CREN
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h
RCREG2
Serial Port Receive Register for USART2
xxxx xxxx
uuuu uuuu
15h
TXSTA2
CSRC
TX9
TXEN
SYNC
TRMT
TX9D
0000 --1x
0000 --1u
16h
TXREG2
Serial Port Transmit Register for USART2
xxxx xxxx
uuuu uuuu
17h
SPBRG2
Baud Rate Generator for USART2
0000 0000
Bank 5:
10h
DDRF
Data Direction Register for PORTF
1111 1111
11h
PORTF(4)
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
0000 0000
12h
DDRG
Data Direction Register for PORTG
1111 1111
13h
PORTG(4)
RG7/
TX2/CK2
RG6/
RX2/DT2
RG5/
PWM3
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
xxxx 0000
uuuu 0000
14h
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 -0-0
15h
ADCON1
ADCS1
ADCS0
ADFM
PCFG3
PCFG2
PCFG1
PCFG0
000- 0000
16h
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
17h
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
MCLR,
WDT
Legend:
x
= unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2:
The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3:
Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4:
This is the value that will be in the port output latch.
5:
When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6:
On any device RESET, these pins are configured as inputs.
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