SSP Address Register in I2" />
參數(shù)資料
型號: PIC17LC752-08/PT
廠商: Microchip Technology
文件頁數(shù): 107/159頁
文件大小: 0K
描述: IC MCU OTP 8KX16 A/D 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: OTP
RAM 容量: 678 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 64-TQFP
包裝: 托盤
PIC17C7XX
DS30289B-page 50
2000 Microchip Technology Inc.
Bank 6
10h
SSPADD
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode
0000 0000
11h
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
12h
SSPCON2
GCEN
AKSTAT
AKDT
AKEN
RCEN
PEN
RSEN
SEN
0000 0000
13h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
14h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
15h
Unimplemented
---- ----
16h
Unimplemented
---- ----
17h
Unimplemented
---- ----
Bank 7
10h
PW3DCL
DC1
DC0
TM2PW3
xx0- ----
uu0- ----
11h
PW3DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
12h
CA3L
Capture3 Low Byte
xxxx xxxx
uuuu uuuu
13h
CA3H
Capture3 High Byte
xxxx xxxx
uuuu uuuu
14h
CA4L
Capture4 Low Byte
xxxx xxxx
uuuu uuuu
15h
CA4H
Capture4 High Byte
xxxx xxxx
uuuu uuuu
16h
TCON3
CA4OVF
CA3OVF
CA4ED1
CA4ED0
CA3ED1
CA3ED0
PWM3ON -000 0000 -000 0000
17h
Unimplemented
---- ----
Bank 8(3)
10h(3)
DDRH
Data Direction Register for PORTH
1111 1111
11h(3)
PORTH(4)
RH7/
AN15
RH6/
AN14
RH5/
AN13
RH4/
AN12
RH3
RH2
RH1
RH0
xxxx xxxx
uuuu uuuu
12h(3)
DDRJ
Data Direction Register for PORTJ
1111 1111
13h(3)
PORTJ(4)
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
xxxx xxxx
uuuu uuuu
14h(3)
Unimplemented
---- ----
15h(3)
Unimplemented
---- ----
16h(3)
Unimplemented
---- ----
17h(3)
Unimplemented
---- ----
Unbanked
18h
PRODL
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx
uuuu uuuu
19h
PRODH
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx
uuuu uuuu
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
MCLR,
WDT
Legend:
x
= unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2:
The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3:
Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4:
This is the value that will be in the port output latch.
5:
When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6:
On any device RESET, these pins are configured as inputs.
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