參數(shù)資料
型號(hào)： PIC17LC44T-08I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 235/241頁(yè)
文件大?。?/td> 0K
描述： IC MCU OTP 8KX16 PWM 44TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 454 x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)當(dāng)前第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)
1996 Microchip Technology Inc.
DS30412C-page 93
PIC17C4X
13.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous
mode
is
entered
by
setting
the
SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to congure the RA5 and RA4 I/O ports
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting the CSRC (TXSTA<7>) bit.
13.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF (PIR<1>) bit is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE
bit (PIE<1>). TXIF will be set regardless of the state of
bit TXIE and cannot be cleared in software. It will reset
only when new data is loaded into TXREG. While TXIF
indicates the status of TXREG, TRMT (TXSTA<1>)
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty. The TSR is not
mapped in data memory, so it is not available to the
user.
Transmission
is
enabled
by
setting
the
TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The rst data
bit will be shifted out on the next available rising edge
of the clock on the RA5/TX/CK pin. Data out is stable
around the falling edge of the synchronous clock
(Figure 13-10). The transmission can also be started
by rst loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is rst started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to
the
TSR,
resulting
in
an
empty
TXREG.
Back-to-back transfers are possible.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RA4/RX/DT and RA5/TX/CK pins will revert to
hi-impedance. If either CREN or SREN are set during
a transmission, the transmission is aborted and the
RA4/RX/DT pin reverts to a hi-impedance state (for a
reception). The RA5/TX/CK pin will remain an output if
the CSRC bit is set (internal clock). The transmitter
logic is not reset, although it is disconnected from the
pins. In order to reset the transmitter, the user has to
clear the TXEN bit. If the SREN bit is set (to interrupt an
ongoing transmission and receive a single word), then
after the single word is received, SREN will be cleared
and the serial port will revert back to transmitting, since
the TXEN bit is still set. The DT line will immediately
switch from hi-impedance receive mode to transmit
and start driving. To avoid this, TXEN should be
cleared.
In
order
to
select
9-bit
transmission,
the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
2.
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
3.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
4.
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
5.
If 9-bit transmission is desired, then set the TX9
bit.
6.
Start transmission by loading data to the
TXREG register.
7.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
8.
Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
proper
state
when
transmit
is
re-enabled.
相關(guān)PDF資料
PDF描述
PIC16F684T-I/SL IC PIC MCU FLASH 2KX14 14SOIC
PIC12HV615-I/P IC PIC MCU FLASH 1KX14 8DIP
PIC17LC44T-08I/L IC MCU OTP 8KX16 PWM 44PLCC
PIC12HV615-I/MF IC PIC MCU FLASH 1KX14 8-DFN
PIC16C774-E/L IC MCU OTP 4KX14 A/D PWM 44PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC17LC752-08/L 功能描述:8位微控制器 -MCU 16KB 678 RAM 50 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17LC752-08/PT 功能描述:8位微控制器 -MCU 16KB 678 RAM 50 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17LC752-08I/L 功能描述:8位微控制器 -MCU 16KB 678 RAM 50 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17LC752-08I/PT 功能描述:8位微控制器 -MCU 16KB 678 RAM 50 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17LC752T-08/L 功能描述:8位微控制器 -MCU 16KB 678 RAM 50 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*