參數(shù)資料
型號： PIC17C766T-33/PT
廠商： Microchip Technology
文件頁數(shù)： 113/159頁
文件大?。?/td> 0K
描述： IC MCU OTP 16KX16 A/D 80TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 33MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： OTP
RAM 容量： 902 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
PIC17C7XX
DS30289B-page 56
2000 Microchip Technology Inc.
7.7
Program Counter Module
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or pro-
gram memory, an 8-bit register PCLATH (PC high
latch) is used as a holding latch for the high byte of the
PC. PCLATH is mapped into data memory. The user
can read or write PCH through PCLATH.
The 16-bit wide PC is incremented after each instruc-
tion fetch during Q1 unless:
Modified by a GOTO, CALL, LCALL, RETURN,
RETLW
, or RETFIE instruction
Modified by an interrupt response
Due to destination write to PCL by an instruction
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
Figure 7-7 and Figure 7-8 show the operation of the
program counter for various situations.
FIGURE 7-7:
PROGRAM COUNTER
OPERATION
FIGURE 7-8:
PROGRAM COUNTER
USING THE CALL AND
GOTO
INSTRUCTIONS
Using Figure 7-7, the operations of the PC and
PCLATH for different instructions are as follows:
a)
LCALL
instructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH
→ PCH
Opcode<7:0>
→ PCL
b)
Read instructions on PCL:
Any instruction that reads PCL.
PCL
→ data bus → ALU or destination
PCH
→ PCLATH
c)
Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data
→ data bus → PCL
PCLATH
→ PCH
d)
Read-Modify-Write instructions on PCL:
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Read:
PCL
→ data bus → ALU
Write:
8-bit result
→ data bus → PCL
PCLATH
→ PCH
e)
RETURN
instruction:
Stack<MRU>
→ PC<15:0>
Using Figure 7-8, the operation of the PC and PCLATH
for GOTO and CALL instructions is as follows:
CALL
, GOTO instructions:
A 13-bit destination address is provided in the
instruction (opcode).
Opcode<12:0>
→ PC<12:0>
PC<15:13>
→ PCLATH<7:5>
Opcode<12:8>
→ PCLATH<4:0>
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH. For
example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
The following PC related operations do not change
PCLATH:
a)
LCALL
, RETLW, and RETFIE instructions.
b)
Interrupt vector is forced onto the PC.
c)
Read-modify-write instructions on PCL
(e.g. BSF PCL).
Internal Data Bus <8>
PCLATH
8
PCH
PCL
8
15
0
7
5 4
0
12
8 7
0
87
PC<15:13>
PCLATH
From Instruction
5
3
8
PCH
PCL
13
15
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