![](http://datasheet.mmic.net.cn/260000/PIC17C42_datasheet_15942894/PIC17C42_230.png)
PIC17C4X
DS30412B-page 230
1996 Microchip Technology Inc.
Figure 6-12:
Program Counter using The CALL and
GOTO Instructions......................................41
BSR Operation (PIC17C43/R43/44)...........42
TLWT Instruction Operation........................43
TABLWT Instruction Operation...................43
TLRD Instruction Operation........................44
TABLRD Instruction Operation ...................44
TABLWT Write Timing (External
Memory)......................................................46
Consecutive TABLWT Write Timing
(External Memory) ......................................47
TABLRD Timing..........................................48
TABLRD Timing (Consecutive TABLRD
Instructions) ................................................48
RA0 and RA1 Block Diagram .....................53
RA2 and RA3 Block Diagram .....................54
RA4 and RA5 Block Diagram .....................54
Block Diagram of RB<7:4> and RB<1:0>
Port Pins .....................................................55
Block Diagram of RB3 and RB2 Port
Pins.............................................................56
Block Diagram of RC<7:0> Port Pins .........58
PORTD Block Diagram (in I/O Port
Mode)..........................................................60
PORTE Block Diagram (in I/O Port
Mode).........................................................62
Successive I/O Operation...........................64
T0STA Register (Address: 05h,
Unbanked) ..................................................67
Timer0 Module Block Diagram ...................68
TMR0 Timing with External Clock
(Increment on Falling Edge) .......................68
TMR0 Timing: Write High or Low
Byte............................................................69
TMR0 Read/Write in Timer Mode...............70
TCON1 Register (Address: 16h,
Bank 3) .......................................................71
TCON2 Register (Address: 17h,
Bank 3) .......................................................72
Timer1 and Timer2 in Two 8-bit
Timer/Counter Mode...................................73
TMR1 and TMR2 in 16-bit
Timer/Counter Mode...................................74
Simplified PWM Block Diagram..................75
PWM Output ...............................................75
Timer3 with One Capture and One
Period Register Block Diagram...................78
Timer3 with Two Capture Registers
Block Diagram ...........................................79
TMR1, TMR2, and TMR3 Operation in
External Clock Mode...................................80
Figure 12-10: TMR1, TMR2, and TMR3 Operation in
Timer Mode.................................................81
Figure 13-1:
TXSTA Register (Address: 15h,
Bank 0) ......................................................83
Figure 13-2:
RCSTA Register (Address: 13h,
Bank 0) .......................................................84
Figure 13-3:
USART Transmit.........................................85
Figure 13-4:
USART Receive..........................................85
Figure 13-5:
Asynchronous Master Transmission...........90
Figure 13-6:
Asynchronous Master Transmission
(Back to Back) ...........................................90
Figure 13-7:
RX Pin Sampling Scheme ..........................91
Figure 13-8:
Asynchronous Reception............................92
Figure 13-9:
Synchronous Transmission ........................94
Figure 13-10: Synchronous Transmission
(Through TXEN) .........................................94
Figure 6-13:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 9-1:
Figure 9-2:
Figure 9-3:
Figure 9-4:
Figure 9-5:
Figure 9-6:
Figure 9-7:
Figure 9-8:
Figure 9-9:
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Figure 12-8:
Figure 12-9:
Figure 13-11: Synchronous Reception (Master
Mode, SREN) ............................................. 95
Figure 14-1:
Configuration Word .................................... 99
Figure 14-2:
Crystal or Ceramic Resonator Operation
(XT or LF OSC Configuration)................. 100
Figure 14-3:
Crystal Operation, Overtone Crystals
(XT OSC Configuration) ........................... 101
Figure 14-4:
External Clock Input Operation
(EC OSC Configuration)........................... 101
Figure 14-5:
External Parallel Resonant Crystal
Oscillator Circuit ....................................... 102
Figure 14-6:
External Series Resonant Crystal
Oscillator Circuit ....................................... 102
Figure 14-7:
RC Oscillator Mode .................................. 102
Figure 14-8:
Watchdog Timer Block Diagram............... 104
Figure 14-9:
Wake-up From Sleep Through
Interrupt.................................................... 105
Figure 15-1:
General Format for Instructions................ 108
Figure 15-2:
Q Cycle Activity ........................................ 109
Figure 16-1:
PICMASTER System
Configuration............................................ 143
Figure 17-1:
Parameter Measurement
Information ............................................... 154
Figure 17-2:
External Clock Timing .............................. 155
Figure 17-3:
CLKOUT and I/O Timing .......................... 156
Figure 17-4:
Reset, Watchdog Timer, Oscillator
Start-Up Timer and Power-Up Timer
Timing....................................................... 157
Figure 17-5:
Timer0 Clock Timings............................... 158
Figure 17-6:
Timer1, Timer2, And Timer3 Clock
Timings..................................................... 158
Figure 17-7:
Capture Timings....................................... 159
Figure 17-8:
PWM Timings........................................... 159
Figure 17-9:
USART Module: Synchronous
Transmission (Master/Slave) Timing........ 160
Figure 17-10: USART Module: Synchronous
Receive (Master/Slave) Timing ................ 160
Figure 17-11: Memory Interface Write Timing ................ 161
Figure 17-12: Memory Interface Read Timing................ 162
Figure 18-1:
Typical RC Oscillator Frequency vs.
Temperature............................................. 163
Figure 18-2:
Typical RC Oscillator Frequency vs.
V
DD
........................................................... 164
Figure 18-3:
Typical RC Oscillator Frequency vs.
V
DD
........................................................... 164
Figure 18-4:
Typical RC Oscillator Frequency vs.
V
DD
........................................................... 165
Figure 18-5:
Transconductance (gm) of LF
Oscillator vs. V
DD
Figure 18-6:
Transconductance (gm) of XT
Oscillator vs. V
DD
Figure 18-7:
Typical I
DD
vs. Frequency (External
Clock 25
°
C)............................................. 167
Figure 18-8:
Maximum I
DD
vs. Frequency (External
Clock 125
°
C to -40
Figure 18-9:
Typical I
PD
vs. V
Disabled 25
°
C .......................................... 168
Figure 18-10: Maximum I
PD
vs. V
Disabled ................................................... 168
Figure 18-11: Typical I
PD
vs. V
Enabled 25
°
C........................................... 169
Figure 18-12: Maximum I
PD
vs. V
Enabled .................................................... 169
Figure 18-13: WDT Timer Time-Out Period vs.
V
DD
........................................................... 170
Figure 18-14: I
OH
vs. V
OH
, V
DD
Figure 18-15: I
OH
vs. V
OH
, V
DD
..................................... 166
..................................... 166
°
Watchdog
C).............................. 167
DD
DD
Watchdog
DD
Watchdog
DD
Watchdog
= 3V.............................. 170
= 5V.............................. 171